1 //===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a wrapper around MCSchedModel that allows the interface to
11 // benefit from information currently only available in TargetInstrInfo.
12 // Ideally, the scheduling interface would be fully defined in the MC layer.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETSCHEDMODEL_H
17 #define LLVM_TARGET_TARGETSCHEDMODEL_H
19 #include "llvm/MC/MCSchedule.h"
20 #include "llvm/MC/MCInstrItineraries.h"
24 class TargetRegisterInfo;
25 class TargetSubtargetInfo;
26 class TargetInstrInfo;
29 /// Provide an instruction scheduling machine model to CodeGen passes.
30 class TargetSchedModel {
31 // For efficiency, hold a copy of the statically defined MCSchedModel for this
33 MCSchedModel SchedModel;
34 InstrItineraryData InstrItins;
35 const TargetSubtargetInfo *STI;
36 const TargetInstrInfo *TII;
38 TargetSchedModel(): STI(0), TII(0) {}
40 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
41 const TargetInstrInfo *tii);
43 const TargetInstrInfo *getInstrInfo() const { return TII; }
45 /// Return true if this machine model includes an instruction-level scheduling
46 /// model. This is more detailed than the course grain IssueWidth and default
47 /// latency properties, but separate from the per-cycle itinerary data.
48 bool hasInstrSchedModel() const {
49 return SchedModel.hasInstrSchedModel();
52 /// Return true if this machine model includes cycle-to-cycle itinerary
53 /// data. This models scheduling at each stage in the processor pipeline.
54 bool hasInstrItineraries() const {
55 return SchedModel.hasInstrItineraries();
58 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }