1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the AARCH64-specific intrinsics.
12 //===----------------------------------------------------------------------===//
14 let TargetPrefix = "aarch64" in {
16 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
18 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
19 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
21 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
22 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
23 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
24 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
25 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
26 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
28 def int_aarch64_clrex : Intrinsic<[]>;
30 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
31 LLVMMatchType<0>], [IntrNoMem]>;
32 def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
33 LLVMMatchType<0>], [IntrNoMem]>;
35 //===----------------------------------------------------------------------===//
38 def int_aarch64_hint : Intrinsic<[], [llvm_i32_ty]>;
40 //===----------------------------------------------------------------------===//
43 def int_aarch64_rbit : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>],
48 //===----------------------------------------------------------------------===//
49 // Advanced SIMD (NEON)
51 let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
52 class AdvSIMD_2Scalar_Float_Intrinsic
53 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
56 class AdvSIMD_FPToIntRounding_Intrinsic
57 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
59 class AdvSIMD_1IntArg_Intrinsic
60 : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
61 class AdvSIMD_1FloatArg_Intrinsic
62 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
63 class AdvSIMD_1VectorArg_Intrinsic
64 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
65 class AdvSIMD_1VectorArg_Expand_Intrinsic
66 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
67 class AdvSIMD_1VectorArg_Long_Intrinsic
68 : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
69 class AdvSIMD_1IntArg_Narrow_Intrinsic
70 : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
71 class AdvSIMD_1VectorArg_Narrow_Intrinsic
72 : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
73 class AdvSIMD_1VectorArg_Int_Across_Intrinsic
74 : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
75 class AdvSIMD_1VectorArg_Float_Across_Intrinsic
76 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
78 class AdvSIMD_2IntArg_Intrinsic
79 : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
81 class AdvSIMD_2FloatArg_Intrinsic
82 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
84 class AdvSIMD_2VectorArg_Intrinsic
85 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
87 class AdvSIMD_2VectorArg_Compare_Intrinsic
88 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
90 class AdvSIMD_2Arg_FloatCompare_Intrinsic
91 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
93 class AdvSIMD_2VectorArg_Long_Intrinsic
94 : Intrinsic<[llvm_anyvector_ty],
95 [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
97 class AdvSIMD_2VectorArg_Wide_Intrinsic
98 : Intrinsic<[llvm_anyvector_ty],
99 [LLVMMatchType<0>, LLVMTruncatedType<0>],
101 class AdvSIMD_2VectorArg_Narrow_Intrinsic
102 : Intrinsic<[llvm_anyvector_ty],
103 [LLVMExtendedType<0>, LLVMExtendedType<0>],
105 class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
106 : Intrinsic<[llvm_anyint_ty],
107 [LLVMExtendedType<0>, llvm_i32_ty],
109 class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
110 : Intrinsic<[llvm_anyvector_ty],
113 class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
114 : Intrinsic<[llvm_anyvector_ty],
115 [LLVMTruncatedType<0>],
117 class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
118 : Intrinsic<[llvm_anyvector_ty],
119 [LLVMTruncatedType<0>, llvm_i32_ty],
121 class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
122 : Intrinsic<[llvm_anyvector_ty],
123 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
126 class AdvSIMD_3VectorArg_Intrinsic
127 : Intrinsic<[llvm_anyvector_ty],
128 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
130 class AdvSIMD_3VectorArg_Scalar_Intrinsic
131 : Intrinsic<[llvm_anyvector_ty],
132 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
134 class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
135 : Intrinsic<[llvm_anyvector_ty],
136 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
137 LLVMMatchType<1>], [IntrNoMem]>;
138 class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
139 : Intrinsic<[llvm_anyvector_ty],
140 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
142 class AdvSIMD_CvtFxToFP_Intrinsic
143 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
145 class AdvSIMD_CvtFPToFx_Intrinsic
146 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
152 let Properties = [IntrNoMem] in {
153 // Vector Add Across Lanes
154 def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
155 def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
156 def int_aarch64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
158 // Vector Long Add Across Lanes
159 def int_aarch64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
160 def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
162 // Vector Halving Add
163 def int_aarch64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
164 def int_aarch64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
166 // Vector Rounding Halving Add
167 def int_aarch64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
168 def int_aarch64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
170 // Vector Saturating Add
171 def int_aarch64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
172 def int_aarch64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
173 def int_aarch64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
174 def int_aarch64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
176 // Vector Add High-Half
177 // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
178 // header is no longer supported.
179 def int_aarch64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
181 // Vector Rounding Add High-Half
182 def int_aarch64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
184 // Vector Saturating Doubling Multiply High
185 def int_aarch64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
187 // Vector Saturating Rounding Doubling Multiply High
188 def int_aarch64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
190 // Vector Polynominal Multiply
191 def int_aarch64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
193 // Vector Long Multiply
194 def int_aarch64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
195 def int_aarch64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
196 def int_aarch64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
198 // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
200 def int_aarch64_neon_pmull64 :
201 Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
203 // Vector Extending Multiply
204 def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
205 let Properties = [IntrNoMem, Commutative];
208 // Vector Saturating Doubling Long Multiply
209 def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
210 def int_aarch64_neon_sqdmulls_scalar
211 : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
213 // Vector Halving Subtract
214 def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
215 def int_aarch64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
217 // Vector Saturating Subtract
218 def int_aarch64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
219 def int_aarch64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
221 // Vector Subtract High-Half
222 // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
223 // header is no longer supported.
224 def int_aarch64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
226 // Vector Rounding Subtract High-Half
227 def int_aarch64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
229 // Vector Compare Absolute Greater-than-or-equal
230 def int_aarch64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
232 // Vector Compare Absolute Greater-than
233 def int_aarch64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
235 // Vector Absolute Difference
236 def int_aarch64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
237 def int_aarch64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
238 def int_aarch64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
240 // Scalar Absolute Difference
241 def int_aarch64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
244 def int_aarch64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
245 def int_aarch64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
246 def int_aarch64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic;
247 def int_aarch64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
249 // Vector Max Across Lanes
250 def int_aarch64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
251 def int_aarch64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
252 def int_aarch64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
253 def int_aarch64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
256 def int_aarch64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
257 def int_aarch64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
258 def int_aarch64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic;
259 def int_aarch64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
261 // Vector Min/Max Number
262 def int_aarch64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
263 def int_aarch64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
265 // Vector Min Across Lanes
266 def int_aarch64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
267 def int_aarch64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
268 def int_aarch64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
269 def int_aarch64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
272 def int_aarch64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
275 // FIXME: In theory, we shouldn't need intrinsics for saddlp or
276 // uaddlp, but tblgen's type inference currently can't handle the
277 // pattern fragments this ends up generating.
278 def int_aarch64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
279 def int_aarch64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
282 def int_aarch64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
283 def int_aarch64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
284 def int_aarch64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
287 def int_aarch64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
288 def int_aarch64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
289 def int_aarch64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
291 // Reciprocal Estimate/Step
292 def int_aarch64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
293 def int_aarch64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
295 // Reciprocal Exponent
296 def int_aarch64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic;
298 // Vector Saturating Shift Left
299 def int_aarch64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
300 def int_aarch64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
302 // Vector Rounding Shift Left
303 def int_aarch64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
304 def int_aarch64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
306 // Vector Saturating Rounding Shift Left
307 def int_aarch64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
308 def int_aarch64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
310 // Vector Signed->Unsigned Shift Left by Constant
311 def int_aarch64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
313 // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
314 def int_aarch64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
316 // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
317 def int_aarch64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
319 // Vector Narrowing Shift Right by Constant
320 def int_aarch64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
321 def int_aarch64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
323 // Vector Rounding Narrowing Shift Right by Constant
324 def int_aarch64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
326 // Vector Rounding Narrowing Saturating Shift Right by Constant
327 def int_aarch64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
328 def int_aarch64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
331 def int_aarch64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
332 def int_aarch64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
334 // Vector Widening Shift Left by Constant
335 def int_aarch64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
336 def int_aarch64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
337 def int_aarch64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
339 // Vector Shift Right by Constant and Insert
340 def int_aarch64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
342 // Vector Shift Left by Constant and Insert
343 def int_aarch64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
345 // Vector Saturating Narrow
346 def int_aarch64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
347 def int_aarch64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
348 def int_aarch64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
349 def int_aarch64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
351 // Vector Saturating Extract and Unsigned Narrow
352 def int_aarch64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
353 def int_aarch64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
355 // Vector Absolute Value
356 def int_aarch64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
358 // Vector Saturating Absolute Value
359 def int_aarch64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
361 // Vector Saturating Negation
362 def int_aarch64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
364 // Vector Count Leading Sign Bits
365 def int_aarch64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
367 // Vector Reciprocal Estimate
368 def int_aarch64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
369 def int_aarch64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic;
371 // Vector Square Root Estimate
372 def int_aarch64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
373 def int_aarch64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic;
375 // Vector Bitwise Reverse
376 def int_aarch64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
378 // Vector Conversions Between Half-Precision and Single-Precision.
379 def int_aarch64_neon_vcvtfp2hf
380 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
381 def int_aarch64_neon_vcvthf2fp
382 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
384 // Vector Conversions Between Floating-point and Fixed-point.
385 def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
386 def int_aarch64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
387 def int_aarch64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
388 def int_aarch64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
390 // Vector FP->Int Conversions
391 def int_aarch64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
392 def int_aarch64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
393 def int_aarch64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
394 def int_aarch64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
395 def int_aarch64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
396 def int_aarch64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
397 def int_aarch64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
398 def int_aarch64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
399 def int_aarch64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
400 def int_aarch64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
402 // Vector FP Rounding: only ties to even is unrepresented by a normal
404 def int_aarch64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
406 // Scalar FP->Int conversions
408 // Vector FP Inexact Narrowing
409 def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
411 // Scalar FP Inexact Narrowing
412 def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
416 let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
417 class AdvSIMD_2Vector2Index_Intrinsic
418 : Intrinsic<[llvm_anyvector_ty],
419 [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
423 // Vector element to element moves
424 def int_aarch64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
426 let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
427 class AdvSIMD_1Vec_Load_Intrinsic
428 : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
430 class AdvSIMD_1Vec_Store_Lane_Intrinsic
431 : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
432 [IntrReadWriteArgMem, NoCapture<2>]>;
434 class AdvSIMD_2Vec_Load_Intrinsic
435 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
436 [LLVMAnyPointerType<LLVMMatchType<0>>],
438 class AdvSIMD_2Vec_Load_Lane_Intrinsic
439 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
440 [LLVMMatchType<0>, LLVMMatchType<0>,
441 llvm_i64_ty, llvm_anyptr_ty],
443 class AdvSIMD_2Vec_Store_Intrinsic
444 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
445 LLVMAnyPointerType<LLVMMatchType<0>>],
446 [IntrReadWriteArgMem, NoCapture<2>]>;
447 class AdvSIMD_2Vec_Store_Lane_Intrinsic
448 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
449 llvm_i64_ty, llvm_anyptr_ty],
450 [IntrReadWriteArgMem, NoCapture<3>]>;
452 class AdvSIMD_3Vec_Load_Intrinsic
453 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
454 [LLVMAnyPointerType<LLVMMatchType<0>>],
456 class AdvSIMD_3Vec_Load_Lane_Intrinsic
457 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
458 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
459 llvm_i64_ty, llvm_anyptr_ty],
461 class AdvSIMD_3Vec_Store_Intrinsic
462 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
463 LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
464 [IntrReadWriteArgMem, NoCapture<3>]>;
465 class AdvSIMD_3Vec_Store_Lane_Intrinsic
466 : Intrinsic<[], [llvm_anyvector_ty,
467 LLVMMatchType<0>, LLVMMatchType<0>,
468 llvm_i64_ty, llvm_anyptr_ty],
469 [IntrReadWriteArgMem, NoCapture<4>]>;
471 class AdvSIMD_4Vec_Load_Intrinsic
472 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
473 LLVMMatchType<0>, LLVMMatchType<0>],
474 [LLVMAnyPointerType<LLVMMatchType<0>>],
476 class AdvSIMD_4Vec_Load_Lane_Intrinsic
477 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
478 LLVMMatchType<0>, LLVMMatchType<0>],
479 [LLVMMatchType<0>, LLVMMatchType<0>,
480 LLVMMatchType<0>, LLVMMatchType<0>,
481 llvm_i64_ty, llvm_anyptr_ty],
483 class AdvSIMD_4Vec_Store_Intrinsic
484 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
485 LLVMMatchType<0>, LLVMMatchType<0>,
486 LLVMAnyPointerType<LLVMMatchType<0>>],
487 [IntrReadWriteArgMem, NoCapture<4>]>;
488 class AdvSIMD_4Vec_Store_Lane_Intrinsic
489 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
490 LLVMMatchType<0>, LLVMMatchType<0>,
491 llvm_i64_ty, llvm_anyptr_ty],
492 [IntrReadWriteArgMem, NoCapture<5>]>;
497 def int_aarch64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
498 def int_aarch64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
499 def int_aarch64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
501 def int_aarch64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
502 def int_aarch64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
503 def int_aarch64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
505 def int_aarch64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
506 def int_aarch64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
507 def int_aarch64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
509 def int_aarch64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
510 def int_aarch64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
511 def int_aarch64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
513 def int_aarch64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
514 def int_aarch64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
515 def int_aarch64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
517 def int_aarch64_neon_st2 : AdvSIMD_2Vec_Store_Intrinsic;
518 def int_aarch64_neon_st3 : AdvSIMD_3Vec_Store_Intrinsic;
519 def int_aarch64_neon_st4 : AdvSIMD_4Vec_Store_Intrinsic;
521 def int_aarch64_neon_st2lane : AdvSIMD_2Vec_Store_Lane_Intrinsic;
522 def int_aarch64_neon_st3lane : AdvSIMD_3Vec_Store_Lane_Intrinsic;
523 def int_aarch64_neon_st4lane : AdvSIMD_4Vec_Store_Lane_Intrinsic;
525 let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
526 class AdvSIMD_Tbl1_Intrinsic
527 : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
529 class AdvSIMD_Tbl2_Intrinsic
530 : Intrinsic<[llvm_anyvector_ty],
531 [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
532 class AdvSIMD_Tbl3_Intrinsic
533 : Intrinsic<[llvm_anyvector_ty],
534 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
537 class AdvSIMD_Tbl4_Intrinsic
538 : Intrinsic<[llvm_anyvector_ty],
539 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
543 class AdvSIMD_Tbx1_Intrinsic
544 : Intrinsic<[llvm_anyvector_ty],
545 [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
547 class AdvSIMD_Tbx2_Intrinsic
548 : Intrinsic<[llvm_anyvector_ty],
549 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
552 class AdvSIMD_Tbx3_Intrinsic
553 : Intrinsic<[llvm_anyvector_ty],
554 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
555 llvm_v16i8_ty, LLVMMatchType<0>],
557 class AdvSIMD_Tbx4_Intrinsic
558 : Intrinsic<[llvm_anyvector_ty],
559 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
560 llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
563 def int_aarch64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
564 def int_aarch64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
565 def int_aarch64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
566 def int_aarch64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
568 def int_aarch64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
569 def int_aarch64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
570 def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
571 def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
573 let TargetPrefix = "aarch64" in {
574 class Crypto_AES_DataKey_Intrinsic
575 : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
577 class Crypto_AES_Data_Intrinsic
578 : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
580 // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
582 class Crypto_SHA_5Hash4Schedule_Intrinsic
583 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
586 // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
588 class Crypto_SHA_1Hash_Intrinsic
589 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
591 // SHA intrinsic taking 8 words of the schedule
592 class Crypto_SHA_8Schedule_Intrinsic
593 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
595 // SHA intrinsic taking 12 words of the schedule
596 class Crypto_SHA_12Schedule_Intrinsic
597 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
600 // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
601 class Crypto_SHA_8Hash4Schedule_Intrinsic
602 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
607 def int_aarch64_crypto_aese : Crypto_AES_DataKey_Intrinsic;
608 def int_aarch64_crypto_aesd : Crypto_AES_DataKey_Intrinsic;
609 def int_aarch64_crypto_aesmc : Crypto_AES_Data_Intrinsic;
610 def int_aarch64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
613 def int_aarch64_crypto_sha1c : Crypto_SHA_5Hash4Schedule_Intrinsic;
614 def int_aarch64_crypto_sha1p : Crypto_SHA_5Hash4Schedule_Intrinsic;
615 def int_aarch64_crypto_sha1m : Crypto_SHA_5Hash4Schedule_Intrinsic;
616 def int_aarch64_crypto_sha1h : Crypto_SHA_1Hash_Intrinsic;
618 def int_aarch64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
619 def int_aarch64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
622 def int_aarch64_crypto_sha256h : Crypto_SHA_8Hash4Schedule_Intrinsic;
623 def int_aarch64_crypto_sha256h2 : Crypto_SHA_8Hash4Schedule_Intrinsic;
624 def int_aarch64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
625 def int_aarch64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
627 //===----------------------------------------------------------------------===//
630 let TargetPrefix = "aarch64" in {
632 def int_aarch64_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
634 def int_aarch64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
636 def int_aarch64_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
638 def int_aarch64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
640 def int_aarch64_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
642 def int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
644 def int_aarch64_crc32x : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
646 def int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],