include/llvm/IR/IntrinsicsAArch64.td

   1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the AARCH64-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let TargetPrefix = "aarch64" in {
  15
  16 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
  17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
  18 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
  19 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
  20
  21 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
  22 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
  23 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
  24                                [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
  25 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
  26                                 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
  27
  28 def int_aarch64_clrex : Intrinsic<[]>;
  29
  30 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  31                                 LLVMMatchType<0>], [IntrNoMem]>;
  32 def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  33                                 LLVMMatchType<0>], [IntrNoMem]>;
  34 }
  35
  36 //===----------------------------------------------------------------------===//
  37 // Advanced SIMD (NEON)
  38
  39 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
  40   class AdvSIMD_2Scalar_Float_Intrinsic
  41     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  42                 [IntrNoMem]>;
  43
  44   class AdvSIMD_FPToIntRounding_Intrinsic
  45     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
  46
  47   class AdvSIMD_1IntArg_Intrinsic
  48     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  49   class AdvSIMD_1FloatArg_Intrinsic
  50     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  51   class AdvSIMD_1VectorArg_Intrinsic
  52     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  53   class AdvSIMD_1VectorArg_Expand_Intrinsic
  54     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  55   class AdvSIMD_1VectorArg_Long_Intrinsic
  56     : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
  57   class AdvSIMD_1IntArg_Narrow_Intrinsic
  58     : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
  59   class AdvSIMD_1VectorArg_Narrow_Intrinsic
  60     : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
  61   class AdvSIMD_1VectorArg_Int_Across_Intrinsic
  62     : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  63   class AdvSIMD_1VectorArg_Float_Across_Intrinsic
  64     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  65
  66   class AdvSIMD_2IntArg_Intrinsic
  67     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  68                 [IntrNoMem]>;
  69   class AdvSIMD_2FloatArg_Intrinsic
  70     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  71                 [IntrNoMem]>;
  72   class AdvSIMD_2VectorArg_Intrinsic
  73     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  74                 [IntrNoMem]>;
  75   class AdvSIMD_2VectorArg_Compare_Intrinsic
  76     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
  77                 [IntrNoMem]>;
  78   class AdvSIMD_2Arg_FloatCompare_Intrinsic
  79     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
  80                 [IntrNoMem]>;
  81   class AdvSIMD_2VectorArg_Long_Intrinsic
  82     : Intrinsic<[llvm_anyvector_ty],
  83                 [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
  84                 [IntrNoMem]>;
  85   class AdvSIMD_2VectorArg_Wide_Intrinsic
  86     : Intrinsic<[llvm_anyvector_ty],
  87                 [LLVMMatchType<0>, LLVMTruncatedType<0>],
  88                 [IntrNoMem]>;
  89   class AdvSIMD_2VectorArg_Narrow_Intrinsic
  90     : Intrinsic<[llvm_anyvector_ty],
  91                 [LLVMExtendedType<0>, LLVMExtendedType<0>],
  92                 [IntrNoMem]>;
  93   class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  94     : Intrinsic<[llvm_anyint_ty],
  95                 [LLVMExtendedType<0>, llvm_i32_ty],
  96                 [IntrNoMem]>;
  97   class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
  98     : Intrinsic<[llvm_anyvector_ty],
  99                 [llvm_anyvector_ty],
 100                 [IntrNoMem]>;
 101   class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
 102     : Intrinsic<[llvm_anyvector_ty],
 103                 [LLVMTruncatedType<0>],
 104                 [IntrNoMem]>;
 105   class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
 106     : Intrinsic<[llvm_anyvector_ty],
 107                 [LLVMTruncatedType<0>, llvm_i32_ty],
 108                 [IntrNoMem]>;
 109   class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
 110     : Intrinsic<[llvm_anyvector_ty],
 111                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
 112                 [IntrNoMem]>;
 113
 114   class AdvSIMD_3VectorArg_Intrinsic
 115       : Intrinsic<[llvm_anyvector_ty],
 116                [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 117                [IntrNoMem]>;
 118   class AdvSIMD_3VectorArg_Scalar_Intrinsic
 119       : Intrinsic<[llvm_anyvector_ty],
 120                [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
 121                [IntrNoMem]>;
 122   class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
 123       : Intrinsic<[llvm_anyvector_ty],
 124                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
 125                 LLVMMatchType<1>], [IntrNoMem]>;
 126   class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
 127     : Intrinsic<[llvm_anyvector_ty],
 128                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
 129                 [IntrNoMem]>;
 130   class AdvSIMD_CvtFxToFP_Intrinsic
 131     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
 132                 [IntrNoMem]>;
 133   class AdvSIMD_CvtFPToFx_Intrinsic
 134     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
 135                 [IntrNoMem]>;
 136 }
 137
 138 // Arithmetic ops
 139
 140 let Properties = [IntrNoMem] in {
 141   // Vector Add Across Lanes
 142   def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 143   def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 144   def int_aarch64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 145
 146   // Vector Long Add Across Lanes
 147   def int_aarch64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 148   def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 149
 150   // Vector Halving Add
 151   def int_aarch64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
 152   def int_aarch64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
 153
 154   // Vector Rounding Halving Add
 155   def int_aarch64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
 156   def int_aarch64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
 157
 158   // Vector Saturating Add
 159   def int_aarch64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
 160   def int_aarch64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
 161   def int_aarch64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
 162   def int_aarch64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
 163
 164   // Vector Add High-Half
 165   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 166   // header is no longer supported.
 167   def int_aarch64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 168
 169   // Vector Rounding Add High-Half
 170   def int_aarch64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 171
 172   // Vector Saturating Doubling Multiply High
 173   def int_aarch64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
 174
 175   // Vector Saturating Rounding Doubling Multiply High
 176   def int_aarch64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
 177
 178   // Vector Polynominal Multiply
 179   def int_aarch64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
 180
 181   // Vector Long Multiply
 182   def int_aarch64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
 183   def int_aarch64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
 184   def int_aarch64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 185
 186   // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
 187   // it with a v16i8.
 188   def int_aarch64_neon_pmull64 :
 189         Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
 190
 191   // Vector Extending Multiply
 192   def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
 193     let Properties = [IntrNoMem, Commutative];
 194   }
 195
 196   // Vector Saturating Doubling Long Multiply
 197   def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 198   def int_aarch64_neon_sqdmulls_scalar
 199     : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 200
 201   // Vector Halving Subtract
 202   def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
 203   def int_aarch64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
 204
 205   // Vector Saturating Subtract
 206   def int_aarch64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
 207   def int_aarch64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
 208
 209   // Vector Subtract High-Half
 210   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 211   // header is no longer supported.
 212   def int_aarch64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 213
 214   // Vector Rounding Subtract High-Half
 215   def int_aarch64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 216
 217   // Vector Compare Absolute Greater-than-or-equal
 218   def int_aarch64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 219
 220   // Vector Compare Absolute Greater-than
 221   def int_aarch64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 222
 223   // Vector Absolute Difference
 224   def int_aarch64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
 225   def int_aarch64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
 226   def int_aarch64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
 227
 228   // Scalar Absolute Difference
 229   def int_aarch64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
 230
 231   // Vector Max
 232   def int_aarch64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
 233   def int_aarch64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
 234   def int_aarch64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic;
 235   def int_aarch64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
 236
 237   // Vector Max Across Lanes
 238   def int_aarch64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 239   def int_aarch64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 240   def int_aarch64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 241   def int_aarch64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 242
 243   // Vector Min
 244   def int_aarch64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
 245   def int_aarch64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
 246   def int_aarch64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic;
 247   def int_aarch64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
 248
 249   // Vector Min/Max Number
 250   def int_aarch64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
 251   def int_aarch64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
 252
 253   // Vector Min Across Lanes
 254   def int_aarch64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 255   def int_aarch64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 256   def int_aarch64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 257   def int_aarch64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 258
 259   // Pairwise Add
 260   def int_aarch64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
 261
 262   // Long Pairwise Add
 263   // FIXME: In theory, we shouldn't need intrinsics for saddlp or
 264   // uaddlp, but tblgen's type inference currently can't handle the
 265   // pattern fragments this ends up generating.
 266   def int_aarch64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 267   def int_aarch64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 268
 269   // Folding Maximum
 270   def int_aarch64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
 271   def int_aarch64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
 272   def int_aarch64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
 273
 274   // Folding Minimum
 275   def int_aarch64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
 276   def int_aarch64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
 277   def int_aarch64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
 278
 279   // Reciprocal Estimate/Step
 280   def int_aarch64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
 281   def int_aarch64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
 282
 283   // Reciprocal Exponent
 284   def int_aarch64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic;
 285
 286   // Vector Saturating Shift Left
 287   def int_aarch64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
 288   def int_aarch64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
 289
 290   // Vector Rounding Shift Left
 291   def int_aarch64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
 292   def int_aarch64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
 293
 294   // Vector Saturating Rounding Shift Left
 295   def int_aarch64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
 296   def int_aarch64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
 297
 298   // Vector Signed->Unsigned Shift Left by Constant
 299   def int_aarch64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
 300
 301   // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
 302   def int_aarch64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 303
 304   // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
 305   def int_aarch64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 306
 307   // Vector Narrowing Shift Right by Constant
 308   def int_aarch64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 309   def int_aarch64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 310
 311   // Vector Rounding Narrowing Shift Right by Constant
 312   def int_aarch64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 313
 314   // Vector Rounding Narrowing Saturating Shift Right by Constant
 315   def int_aarch64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 316   def int_aarch64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 317
 318   // Vector Shift Left
 319   def int_aarch64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
 320   def int_aarch64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
 321
 322   // Vector Widening Shift Left by Constant
 323   def int_aarch64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
 324   def int_aarch64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 325   def int_aarch64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 326
 327   // Vector Shift Right by Constant and Insert
 328   def int_aarch64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 329
 330   // Vector Shift Left by Constant and Insert
 331   def int_aarch64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 332
 333   // Vector Saturating Narrow
 334   def int_aarch64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
 335   def int_aarch64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
 336   def int_aarch64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 337   def int_aarch64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 338
 339   // Vector Saturating Extract and Unsigned Narrow
 340   def int_aarch64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
 341   def int_aarch64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 342
 343   // Vector Absolute Value
 344   def int_aarch64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
 345
 346   // Vector Saturating Absolute Value
 347   def int_aarch64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
 348
 349   // Vector Saturating Negation
 350   def int_aarch64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
 351
 352   // Vector Count Leading Sign Bits
 353   def int_aarch64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
 354
 355   // Vector Reciprocal Estimate
 356   def int_aarch64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
 357   def int_aarch64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic;
 358
 359   // Vector Square Root Estimate
 360   def int_aarch64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
 361   def int_aarch64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic;
 362
 363   // Vector Bitwise Reverse
 364   def int_aarch64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
 365
 366   // Vector Conversions Between Half-Precision and Single-Precision.
 367   def int_aarch64_neon_vcvtfp2hf
 368     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 369   def int_aarch64_neon_vcvthf2fp
 370     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 371
 372   // Vector Conversions Between Floating-point and Fixed-point.
 373   def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
 374   def int_aarch64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
 375   def int_aarch64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 376   def int_aarch64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 377
 378   // Vector FP->Int Conversions
 379   def int_aarch64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
 380   def int_aarch64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
 381   def int_aarch64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
 382   def int_aarch64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
 383   def int_aarch64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
 384   def int_aarch64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
 385   def int_aarch64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
 386   def int_aarch64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
 387   def int_aarch64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
 388   def int_aarch64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
 389
 390   // Vector FP Rounding: only ties to even is unrepresented by a normal
 391   // intrinsic.
 392   def int_aarch64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
 393
 394   // Scalar FP->Int conversions
 395
 396   // Vector FP Inexact Narrowing
 397   def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
 398
 399   // Scalar FP Inexact Narrowing
 400   def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
 401                                         [IntrNoMem]>;
 402 }
 403
 404 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 405   class AdvSIMD_2Vector2Index_Intrinsic
 406     : Intrinsic<[llvm_anyvector_ty],
 407                 [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
 408                 [IntrNoMem]>;
 409 }
 410
 411 // Vector element to element moves
 412 def int_aarch64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
 413
 414 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 415   class AdvSIMD_1Vec_Load_Intrinsic
 416       : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
 417                   [IntrReadArgMem]>;
 418   class AdvSIMD_1Vec_Store_Lane_Intrinsic
 419     : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
 420                 [IntrReadWriteArgMem, NoCapture<2>]>;
 421
 422   class AdvSIMD_2Vec_Load_Intrinsic
 423     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 424                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 425                 [IntrReadArgMem]>;
 426   class AdvSIMD_2Vec_Load_Lane_Intrinsic
 427     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 428                 [LLVMMatchType<0>, LLVMMatchType<0>,
 429                  llvm_i64_ty, llvm_anyptr_ty],
 430                 [IntrReadArgMem]>;
 431   class AdvSIMD_2Vec_Store_Intrinsic
 432     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 433                      LLVMAnyPointerType<LLVMMatchType<0>>],
 434                 [IntrReadWriteArgMem, NoCapture<2>]>;
 435   class AdvSIMD_2Vec_Store_Lane_Intrinsic
 436     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 437                  llvm_i64_ty, llvm_anyptr_ty],
 438                 [IntrReadWriteArgMem, NoCapture<3>]>;
 439
 440   class AdvSIMD_3Vec_Load_Intrinsic
 441     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 442                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 443                 [IntrReadArgMem]>;
 444   class AdvSIMD_3Vec_Load_Lane_Intrinsic
 445     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 446                 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
 447                  llvm_i64_ty, llvm_anyptr_ty],
 448                 [IntrReadArgMem]>;
 449   class AdvSIMD_3Vec_Store_Intrinsic
 450     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 451                      LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
 452                 [IntrReadWriteArgMem, NoCapture<3>]>;
 453   class AdvSIMD_3Vec_Store_Lane_Intrinsic
 454     : Intrinsic<[], [llvm_anyvector_ty,
 455                  LLVMMatchType<0>, LLVMMatchType<0>,
 456                  llvm_i64_ty, llvm_anyptr_ty],
 457                 [IntrReadWriteArgMem, NoCapture<4>]>;
 458
 459   class AdvSIMD_4Vec_Load_Intrinsic
 460     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 461                  LLVMMatchType<0>, LLVMMatchType<0>],
 462                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 463                 [IntrReadArgMem]>;
 464   class AdvSIMD_4Vec_Load_Lane_Intrinsic
 465     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 466                  LLVMMatchType<0>, LLVMMatchType<0>],
 467                 [LLVMMatchType<0>, LLVMMatchType<0>,
 468                  LLVMMatchType<0>, LLVMMatchType<0>,
 469                  llvm_i64_ty, llvm_anyptr_ty],
 470                 [IntrReadArgMem]>;
 471   class AdvSIMD_4Vec_Store_Intrinsic
 472     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 473                  LLVMMatchType<0>, LLVMMatchType<0>,
 474                  LLVMAnyPointerType<LLVMMatchType<0>>],
 475                 [IntrReadWriteArgMem, NoCapture<4>]>;
 476   class AdvSIMD_4Vec_Store_Lane_Intrinsic
 477     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 478                  LLVMMatchType<0>, LLVMMatchType<0>,
 479                  llvm_i64_ty, llvm_anyptr_ty],
 480                 [IntrReadWriteArgMem, NoCapture<5>]>;
 481 }
 482
 483 // Memory ops
 484
 485 def int_aarch64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
 486 def int_aarch64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
 487 def int_aarch64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
 488
 489 def int_aarch64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
 490 def int_aarch64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
 491 def int_aarch64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
 492
 493 def int_aarch64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
 494 def int_aarch64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
 495 def int_aarch64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
 496
 497 def int_aarch64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
 498 def int_aarch64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
 499 def int_aarch64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
 500
 501 def int_aarch64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
 502 def int_aarch64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
 503 def int_aarch64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
 504
 505 def int_aarch64_neon_st2  : AdvSIMD_2Vec_Store_Intrinsic;
 506 def int_aarch64_neon_st3  : AdvSIMD_3Vec_Store_Intrinsic;
 507 def int_aarch64_neon_st4  : AdvSIMD_4Vec_Store_Intrinsic;
 508
 509 def int_aarch64_neon_st2lane  : AdvSIMD_2Vec_Store_Lane_Intrinsic;
 510 def int_aarch64_neon_st3lane  : AdvSIMD_3Vec_Store_Lane_Intrinsic;
 511 def int_aarch64_neon_st4lane  : AdvSIMD_4Vec_Store_Lane_Intrinsic;
 512
 513 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 514   class AdvSIMD_Tbl1_Intrinsic
 515     : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
 516                 [IntrNoMem]>;
 517   class AdvSIMD_Tbl2_Intrinsic
 518     : Intrinsic<[llvm_anyvector_ty],
 519                 [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
 520   class AdvSIMD_Tbl3_Intrinsic
 521     : Intrinsic<[llvm_anyvector_ty],
 522                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 523                  LLVMMatchType<0>],
 524                 [IntrNoMem]>;
 525   class AdvSIMD_Tbl4_Intrinsic
 526     : Intrinsic<[llvm_anyvector_ty],
 527                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 528                  LLVMMatchType<0>],
 529                 [IntrNoMem]>;
 530
 531   class AdvSIMD_Tbx1_Intrinsic
 532     : Intrinsic<[llvm_anyvector_ty],
 533                 [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
 534                 [IntrNoMem]>;
 535   class AdvSIMD_Tbx2_Intrinsic
 536     : Intrinsic<[llvm_anyvector_ty],
 537                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 538                  LLVMMatchType<0>],
 539                 [IntrNoMem]>;
 540   class AdvSIMD_Tbx3_Intrinsic
 541     : Intrinsic<[llvm_anyvector_ty],
 542                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 543                  llvm_v16i8_ty, LLVMMatchType<0>],
 544                 [IntrNoMem]>;
 545   class AdvSIMD_Tbx4_Intrinsic
 546     : Intrinsic<[llvm_anyvector_ty],
 547                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 548                  llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
 549                 [IntrNoMem]>;
 550 }
 551 def int_aarch64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
 552 def int_aarch64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
 553 def int_aarch64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
 554 def int_aarch64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
 555
 556 def int_aarch64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
 557 def int_aarch64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
 558 def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
 559 def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
 560
 561 let TargetPrefix = "aarch64" in {
 562   class Crypto_AES_DataKey_Intrinsic
 563     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
 564
 565   class Crypto_AES_Data_Intrinsic
 566     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
 567
 568   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 569   // (v4i32).
 570   class Crypto_SHA_5Hash4Schedule_Intrinsic
 571     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 572                 [IntrNoMem]>;
 573
 574   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 575   // (v4i32).
 576   class Crypto_SHA_1Hash_Intrinsic
 577     : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 578
 579   // SHA intrinsic taking 8 words of the schedule
 580   class Crypto_SHA_8Schedule_Intrinsic
 581     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
 582
 583   // SHA intrinsic taking 12 words of the schedule
 584   class Crypto_SHA_12Schedule_Intrinsic
 585     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 586                 [IntrNoMem]>;
 587
 588   // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
 589   class Crypto_SHA_8Hash4Schedule_Intrinsic
 590     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 591                 [IntrNoMem]>;
 592 }
 593
 594 // AES
 595 def int_aarch64_crypto_aese   : Crypto_AES_DataKey_Intrinsic;
 596 def int_aarch64_crypto_aesd   : Crypto_AES_DataKey_Intrinsic;
 597 def int_aarch64_crypto_aesmc  : Crypto_AES_Data_Intrinsic;
 598 def int_aarch64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
 599
 600 // SHA1
 601 def int_aarch64_crypto_sha1c  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 602 def int_aarch64_crypto_sha1p  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 603 def int_aarch64_crypto_sha1m  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 604 def int_aarch64_crypto_sha1h  : Crypto_SHA_1Hash_Intrinsic;
 605
 606 def int_aarch64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
 607 def int_aarch64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
 608
 609 // SHA256
 610 def int_aarch64_crypto_sha256h   : Crypto_SHA_8Hash4Schedule_Intrinsic;
 611 def int_aarch64_crypto_sha256h2  : Crypto_SHA_8Hash4Schedule_Intrinsic;
 612 def int_aarch64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
 613 def int_aarch64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
 614
 615 //===----------------------------------------------------------------------===//
 616 // CRC32
 617
 618 let TargetPrefix = "aarch64" in {
 619
 620 def int_aarch64_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 621     [IntrNoMem]>;
 622 def int_aarch64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 623     [IntrNoMem]>;
 624 def int_aarch64_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 625     [IntrNoMem]>;
 626 def int_aarch64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 627     [IntrNoMem]>;
 628 def int_aarch64_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 629     [IntrNoMem]>;
 630 def int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 631     [IntrNoMem]>;
 632 def int_aarch64_crc32x  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 633     [IntrNoMem]>;
 634 def int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 635     [IntrNoMem]>;
 636 }