1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
21 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
27 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
28 [IntrNoMem, Commutative]>;
29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
30 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
32 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
34 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
36 //===----------------------------------------------------------------------===//
37 // Load, Store and Clear exclusive
39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
41 def int_arm_clrex : Intrinsic<[]>;
43 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
45 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
47 //===----------------------------------------------------------------------===//
48 // Data barrier instructions
49 def int_arm_dmb : Intrinsic<[], [llvm_i32_ty]>;
50 def int_arm_dsb : Intrinsic<[], [llvm_i32_ty]>;
52 //===----------------------------------------------------------------------===//
55 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
56 Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
57 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
58 Intrinsic<[], [llvm_i32_ty], []>;
59 def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
61 def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
64 //===----------------------------------------------------------------------===//
67 // Move to coprocessor
68 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
69 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
70 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
71 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
72 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
73 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
75 // Move from coprocessor
76 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
77 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
78 llvm_i32_ty, llvm_i32_ty], []>;
79 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
80 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
81 llvm_i32_ty, llvm_i32_ty], []>;
83 // Coprocessor data processing
84 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
85 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
86 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
87 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
88 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
89 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
91 // Move from two registers to coprocessor
92 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
93 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
94 llvm_i32_ty, llvm_i32_ty], []>;
95 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
96 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
97 llvm_i32_ty, llvm_i32_ty], []>;
99 //===----------------------------------------------------------------------===//
102 def int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
104 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
106 def int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
108 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
110 def int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
112 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
115 //===----------------------------------------------------------------------===//
117 def int_arm_sevl : Intrinsic<[], []>;
119 //===----------------------------------------------------------------------===//
120 // Advanced SIMD (NEON)
122 // The following classes do not correspond directly to GCC builtins.
123 class Neon_1Arg_Intrinsic
124 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
125 class Neon_1Arg_Narrow_Intrinsic
126 : Intrinsic<[llvm_anyvector_ty],
127 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
128 class Neon_2Arg_Intrinsic
129 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
131 class Neon_2Arg_Narrow_Intrinsic
132 : Intrinsic<[llvm_anyvector_ty],
133 [LLVMExtendedElementVectorType<0>,
134 LLVMExtendedElementVectorType<0>],
136 class Neon_2Arg_Long_Intrinsic
137 : Intrinsic<[llvm_anyvector_ty],
138 [LLVMTruncatedElementVectorType<0>,
139 LLVMTruncatedElementVectorType<0>],
141 class Neon_3Arg_Intrinsic
142 : Intrinsic<[llvm_anyvector_ty],
143 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
145 class Neon_3Arg_Long_Intrinsic
146 : Intrinsic<[llvm_anyvector_ty],
148 LLVMTruncatedElementVectorType<0>,
149 LLVMTruncatedElementVectorType<0>],
151 class Neon_CvtFxToFP_Intrinsic
152 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
153 class Neon_CvtFPToFx_Intrinsic
154 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
155 class Neon_CvtFPtoInt_1Arg_Intrinsic
156 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
158 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
159 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
160 // Overall, the classes range from 2 to 6 v8i8 arguments.
161 class Neon_Tbl2Arg_Intrinsic
162 : Intrinsic<[llvm_v8i8_ty],
163 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
164 class Neon_Tbl3Arg_Intrinsic
165 : Intrinsic<[llvm_v8i8_ty],
166 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
167 class Neon_Tbl4Arg_Intrinsic
168 : Intrinsic<[llvm_v8i8_ty],
169 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
171 class Neon_Tbl5Arg_Intrinsic
172 : Intrinsic<[llvm_v8i8_ty],
173 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
174 llvm_v8i8_ty], [IntrNoMem]>;
175 class Neon_Tbl6Arg_Intrinsic
176 : Intrinsic<[llvm_v8i8_ty],
177 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
178 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
182 let Properties = [IntrNoMem, Commutative] in {
185 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
186 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
187 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
188 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
189 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
190 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
191 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
194 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
195 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
196 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
197 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
198 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
199 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
200 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
203 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
204 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
205 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
208 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
209 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
210 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
212 // Vector Reciprocal Step.
213 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
215 // Vector Reciprocal Square Root Step.
216 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
220 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
221 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
222 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
223 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
224 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
226 // Vector Absolute Compare.
227 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
228 [llvm_v2f32_ty, llvm_v2f32_ty],
230 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
231 [llvm_v4f32_ty, llvm_v4f32_ty],
233 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
234 [llvm_v2f32_ty, llvm_v2f32_ty],
236 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
237 [llvm_v4f32_ty, llvm_v4f32_ty],
240 // Vector Absolute Differences.
241 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
242 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
244 // Vector Pairwise Add.
245 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
247 // Vector Pairwise Add Long.
248 // Note: This is different than the other "long" NEON intrinsics because
249 // the result vector has half as many elements as the source vector.
250 // The source and destination vector types must be specified separately.
251 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
253 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
256 // Vector Pairwise Add and Accumulate Long.
257 // Note: This is similar to vpaddl but the destination vector also appears
258 // as the first argument.
259 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
260 [LLVMMatchType<0>, llvm_anyvector_ty],
262 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
263 [LLVMMatchType<0>, llvm_anyvector_ty],
266 // Vector Pairwise Maximum and Minimum.
267 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
268 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
269 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
270 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
274 // The various saturating and rounding vector shift operations need to be
275 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
276 // operation cannot be safely translated to LLVM's shift operators. VSHL can
277 // be used for both left and right shifts, or even combinations of the two,
278 // depending on the signs of the shift amounts. It also has well-defined
279 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
280 // by constants can be represented with LLVM's shift operators.
282 // The shift counts for these intrinsics are always vectors, even for constant
283 // shifts, where the constant is replicated. For consistency with VSHL (and
284 // other variable shift instructions), left shifts have positive shift counts
285 // and right shifts have negative shift counts. This convention is also used
286 // for constant right shift intrinsics, and to help preserve sanity, the
287 // intrinsic names use "shift" instead of either "shl" or "shr". Where
288 // applicable, signed and unsigned versions of the intrinsics are
289 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
290 // such as VQSHLU, take signed operands but produce unsigned results; these
291 // use a "su" suffix.
294 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
295 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
296 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
297 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
298 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
300 // Vector Rounding Shift.
301 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
302 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
303 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
305 // Vector Saturating Shift.
306 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
307 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
308 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
309 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
310 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
311 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
313 // Vector Saturating Rounding Shift.
314 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
315 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
316 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
317 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
318 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
320 // Vector Shift and Insert.
321 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
323 // Vector Absolute Value and Saturating Absolute Value.
324 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
325 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
327 // Vector Saturating Negate.
328 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
330 // Vector Count Leading Sign/Zero Bits.
331 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
332 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
334 // Vector Count One Bits.
335 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
337 // Vector Reciprocal Estimate.
338 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
340 // Vector Reciprocal Square Root Estimate.
341 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
343 // Vector Conversions Between Floating-point and Integer
344 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
345 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
346 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
347 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
348 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
349 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
350 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
351 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
353 // Vector Conversions Between Floating-point and Fixed-point.
354 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
355 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
356 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
357 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
359 // Vector Conversions Between Half-Precision and Single-Precision.
360 def int_arm_neon_vcvtfp2hf
361 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
362 def int_arm_neon_vcvthf2fp
363 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
365 // Narrowing Saturating Vector Moves.
366 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
367 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
368 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
370 // Vector Table Lookup.
371 // The first 1-4 arguments are the table.
372 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
373 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
374 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
375 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
377 // Vector Table Extension.
378 // Some elements of the destination vector may not be updated, so the original
379 // value of that vector is passed as the first argument. The next 1-4
380 // arguments after that are the table.
381 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
382 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
383 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
384 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
387 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
388 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
389 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
390 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
391 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
392 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
394 // De-interleaving vector loads from N-element structures.
395 // Source operands are the address and alignment.
396 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
397 [llvm_ptr_ty, llvm_i32_ty],
399 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
400 [llvm_ptr_ty, llvm_i32_ty],
402 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
404 [llvm_ptr_ty, llvm_i32_ty],
406 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
407 LLVMMatchType<0>, LLVMMatchType<0>],
408 [llvm_ptr_ty, llvm_i32_ty],
411 // Vector load N-element structure to one lane.
412 // Source operands are: the address, the N input vectors (since only one
413 // lane is assigned), the lane number, and the alignment.
414 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
415 [llvm_ptr_ty, LLVMMatchType<0>,
416 LLVMMatchType<0>, llvm_i32_ty,
417 llvm_i32_ty], [IntrReadArgMem]>;
418 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
420 [llvm_ptr_ty, LLVMMatchType<0>,
421 LLVMMatchType<0>, LLVMMatchType<0>,
422 llvm_i32_ty, llvm_i32_ty],
424 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
425 LLVMMatchType<0>, LLVMMatchType<0>],
426 [llvm_ptr_ty, LLVMMatchType<0>,
427 LLVMMatchType<0>, LLVMMatchType<0>,
428 LLVMMatchType<0>, llvm_i32_ty,
429 llvm_i32_ty], [IntrReadArgMem]>;
431 // Interleaving vector stores from N-element structures.
432 // Source operands are: the address, the N vectors, and the alignment.
433 def int_arm_neon_vst1 : Intrinsic<[],
434 [llvm_ptr_ty, llvm_anyvector_ty,
435 llvm_i32_ty], [IntrReadWriteArgMem]>;
436 def int_arm_neon_vst2 : Intrinsic<[],
437 [llvm_ptr_ty, llvm_anyvector_ty,
438 LLVMMatchType<0>, llvm_i32_ty],
439 [IntrReadWriteArgMem]>;
440 def int_arm_neon_vst3 : Intrinsic<[],
441 [llvm_ptr_ty, llvm_anyvector_ty,
442 LLVMMatchType<0>, LLVMMatchType<0>,
443 llvm_i32_ty], [IntrReadWriteArgMem]>;
444 def int_arm_neon_vst4 : Intrinsic<[],
445 [llvm_ptr_ty, llvm_anyvector_ty,
446 LLVMMatchType<0>, LLVMMatchType<0>,
447 LLVMMatchType<0>, llvm_i32_ty],
448 [IntrReadWriteArgMem]>;
450 // Vector store N-element structure from one lane.
451 // Source operands are: the address, the N vectors, the lane number, and
453 def int_arm_neon_vst2lane : Intrinsic<[],
454 [llvm_ptr_ty, llvm_anyvector_ty,
455 LLVMMatchType<0>, llvm_i32_ty,
456 llvm_i32_ty], [IntrReadWriteArgMem]>;
457 def int_arm_neon_vst3lane : Intrinsic<[],
458 [llvm_ptr_ty, llvm_anyvector_ty,
459 LLVMMatchType<0>, LLVMMatchType<0>,
460 llvm_i32_ty, llvm_i32_ty],
461 [IntrReadWriteArgMem]>;
462 def int_arm_neon_vst4lane : Intrinsic<[],
463 [llvm_ptr_ty, llvm_anyvector_ty,
464 LLVMMatchType<0>, LLVMMatchType<0>,
465 LLVMMatchType<0>, llvm_i32_ty,
466 llvm_i32_ty], [IntrReadWriteArgMem]>;
468 // Vector bitwise select.
469 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
470 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
474 // Crypto instructions
475 def int_arm_neon_aesd : Neon_2Arg_Intrinsic;
476 def int_arm_neon_aese : Neon_2Arg_Intrinsic;
477 def int_arm_neon_aesimc : Neon_1Arg_Intrinsic;
478 def int_arm_neon_aesmc : Neon_1Arg_Intrinsic;
479 def int_arm_neon_sha1h : Neon_1Arg_Intrinsic;
480 def int_arm_neon_sha1su1 : Neon_2Arg_Intrinsic;
481 def int_arm_neon_sha256su0 : Neon_2Arg_Intrinsic;
482 def int_arm_neon_sha1c : Neon_3Arg_Intrinsic;
483 def int_arm_neon_sha1m : Neon_3Arg_Intrinsic;
484 def int_arm_neon_sha1p : Neon_3Arg_Intrinsic;
485 def int_arm_neon_sha1su0: Neon_3Arg_Intrinsic;
486 def int_arm_neon_sha256h: Neon_3Arg_Intrinsic;
487 def int_arm_neon_sha256h2: Neon_3Arg_Intrinsic;
488 def int_arm_neon_sha256su1: Neon_3Arg_Intrinsic;
490 } // end TargetPrefix