1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
21 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
27 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
28 [IntrNoMem, Commutative]>;
29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
30 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
32 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
34 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
36 //===----------------------------------------------------------------------===//
37 // Load, Store and Clear exclusive
39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
42 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
43 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
45 def int_arm_clrex : Intrinsic<[]>;
47 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
49 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
51 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
52 [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
53 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
55 //===----------------------------------------------------------------------===//
56 // Data barrier instructions
57 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>;
58 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_ty]>;
60 //===----------------------------------------------------------------------===//
63 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
64 Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
65 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
66 Intrinsic<[], [llvm_i32_ty], []>;
67 def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
69 def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
72 //===----------------------------------------------------------------------===//
75 // Move to coprocessor
76 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
77 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
78 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
79 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
80 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
81 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
83 // Move from coprocessor
84 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
85 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
86 llvm_i32_ty, llvm_i32_ty], []>;
87 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
88 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
89 llvm_i32_ty, llvm_i32_ty], []>;
91 // Coprocessor data processing
92 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
93 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
94 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
95 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
96 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
97 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
99 // Move from two registers to coprocessor
100 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
101 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
102 llvm_i32_ty, llvm_i32_ty], []>;
103 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
104 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
105 llvm_i32_ty, llvm_i32_ty], []>;
107 //===----------------------------------------------------------------------===//
110 def int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
112 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
114 def int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
116 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
118 def int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
120 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
123 //===----------------------------------------------------------------------===//
125 def int_arm_sevl : Intrinsic<[], []>;
127 //===----------------------------------------------------------------------===//
128 // Advanced SIMD (NEON)
130 // The following classes do not correspond directly to GCC builtins.
131 class Neon_1Arg_Intrinsic
132 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
133 class Neon_1Arg_Narrow_Intrinsic
134 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
135 class Neon_2Arg_Intrinsic
136 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
138 class Neon_2Arg_Narrow_Intrinsic
139 : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
141 class Neon_2Arg_Long_Intrinsic
142 : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
144 class Neon_3Arg_Intrinsic
145 : Intrinsic<[llvm_anyvector_ty],
146 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
148 class Neon_3Arg_Long_Intrinsic
149 : Intrinsic<[llvm_anyvector_ty],
150 [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
152 class Neon_CvtFxToFP_Intrinsic
153 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
154 class Neon_CvtFPToFx_Intrinsic
155 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
156 class Neon_CvtFPtoInt_1Arg_Intrinsic
157 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
159 class Neon_Compare_Intrinsic
160 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
163 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
164 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
165 // Overall, the classes range from 2 to 6 v8i8 arguments.
166 class Neon_Tbl2Arg_Intrinsic
167 : Intrinsic<[llvm_v8i8_ty],
168 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
169 class Neon_Tbl3Arg_Intrinsic
170 : Intrinsic<[llvm_v8i8_ty],
171 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
172 class Neon_Tbl4Arg_Intrinsic
173 : Intrinsic<[llvm_v8i8_ty],
174 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
176 class Neon_Tbl5Arg_Intrinsic
177 : Intrinsic<[llvm_v8i8_ty],
178 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
179 llvm_v8i8_ty], [IntrNoMem]>;
180 class Neon_Tbl6Arg_Intrinsic
181 : Intrinsic<[llvm_v8i8_ty],
182 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
183 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
187 let Properties = [IntrNoMem, Commutative] in {
190 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
191 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
192 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
193 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
194 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
195 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
196 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
199 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
200 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
201 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
202 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
203 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
204 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
205 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
208 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
209 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
210 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
213 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
214 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
215 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
217 // Vector Reciprocal Step.
218 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
220 // Vector Reciprocal Square Root Step.
221 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
225 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
226 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
227 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
228 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
229 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
231 // Vector Absolute Compare.
232 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
233 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
235 // Vector Absolute Differences.
236 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
237 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
239 // Vector Pairwise Add.
240 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
242 // Vector Pairwise Add Long.
243 // Note: This is different than the other "long" NEON intrinsics because
244 // the result vector has half as many elements as the source vector.
245 // The source and destination vector types must be specified separately.
246 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
248 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
251 // Vector Pairwise Add and Accumulate Long.
252 // Note: This is similar to vpaddl but the destination vector also appears
253 // as the first argument.
254 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
255 [LLVMMatchType<0>, llvm_anyvector_ty],
257 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
258 [LLVMMatchType<0>, llvm_anyvector_ty],
261 // Vector Pairwise Maximum and Minimum.
262 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
263 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
264 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
265 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
269 // The various saturating and rounding vector shift operations need to be
270 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
271 // operation cannot be safely translated to LLVM's shift operators. VSHL can
272 // be used for both left and right shifts, or even combinations of the two,
273 // depending on the signs of the shift amounts. It also has well-defined
274 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
275 // by constants can be represented with LLVM's shift operators.
277 // The shift counts for these intrinsics are always vectors, even for constant
278 // shifts, where the constant is replicated. For consistency with VSHL (and
279 // other variable shift instructions), left shifts have positive shift counts
280 // and right shifts have negative shift counts. This convention is also used
281 // for constant right shift intrinsics, and to help preserve sanity, the
282 // intrinsic names use "shift" instead of either "shl" or "shr". Where
283 // applicable, signed and unsigned versions of the intrinsics are
284 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
285 // such as VQSHLU, take signed operands but produce unsigned results; these
286 // use a "su" suffix.
289 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
290 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
292 // Vector Rounding Shift.
293 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
294 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
295 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
297 // Vector Saturating Shift.
298 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
299 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
300 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
301 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
302 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
303 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
305 // Vector Saturating Rounding Shift.
306 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
307 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
308 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
309 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
310 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
312 // Vector Shift and Insert.
313 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
315 // Vector Absolute Value and Saturating Absolute Value.
316 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
317 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
319 // Vector Saturating Negate.
320 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
322 // Vector Count Leading Sign/Zero Bits.
323 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
324 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
326 // Vector Count One Bits.
327 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
329 // Vector Reciprocal Estimate.
330 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
332 // Vector Reciprocal Square Root Estimate.
333 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
335 // Vector Conversions Between Floating-point and Integer
336 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
337 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
338 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
339 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
340 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
341 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
342 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
343 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
345 // Vector Conversions Between Floating-point and Fixed-point.
346 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
347 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
348 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
349 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
351 // Vector Conversions Between Half-Precision and Single-Precision.
352 def int_arm_neon_vcvtfp2hf
353 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
354 def int_arm_neon_vcvthf2fp
355 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
357 // Narrowing Saturating Vector Moves.
358 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
359 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
360 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
362 // Vector Table Lookup.
363 // The first 1-4 arguments are the table.
364 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
365 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
366 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
367 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
369 // Vector Table Extension.
370 // Some elements of the destination vector may not be updated, so the original
371 // value of that vector is passed as the first argument. The next 1-4
372 // arguments after that are the table.
373 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
374 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
375 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
376 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
379 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
380 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
381 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
382 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
383 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
384 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
386 // De-interleaving vector loads from N-element structures.
387 // Source operands are the address and alignment.
388 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
389 [llvm_ptr_ty, llvm_i32_ty],
391 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
392 [llvm_ptr_ty, llvm_i32_ty],
394 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
396 [llvm_ptr_ty, llvm_i32_ty],
398 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
399 LLVMMatchType<0>, LLVMMatchType<0>],
400 [llvm_ptr_ty, llvm_i32_ty],
403 // Vector load N-element structure to one lane.
404 // Source operands are: the address, the N input vectors (since only one
405 // lane is assigned), the lane number, and the alignment.
406 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
407 [llvm_ptr_ty, LLVMMatchType<0>,
408 LLVMMatchType<0>, llvm_i32_ty,
409 llvm_i32_ty], [IntrReadArgMem]>;
410 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
412 [llvm_ptr_ty, LLVMMatchType<0>,
413 LLVMMatchType<0>, LLVMMatchType<0>,
414 llvm_i32_ty, llvm_i32_ty],
416 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
417 LLVMMatchType<0>, LLVMMatchType<0>],
418 [llvm_ptr_ty, LLVMMatchType<0>,
419 LLVMMatchType<0>, LLVMMatchType<0>,
420 LLVMMatchType<0>, llvm_i32_ty,
421 llvm_i32_ty], [IntrReadArgMem]>;
423 // Interleaving vector stores from N-element structures.
424 // Source operands are: the address, the N vectors, and the alignment.
425 def int_arm_neon_vst1 : Intrinsic<[],
426 [llvm_ptr_ty, llvm_anyvector_ty,
427 llvm_i32_ty], [IntrReadWriteArgMem]>;
428 def int_arm_neon_vst2 : Intrinsic<[],
429 [llvm_ptr_ty, llvm_anyvector_ty,
430 LLVMMatchType<0>, llvm_i32_ty],
431 [IntrReadWriteArgMem]>;
432 def int_arm_neon_vst3 : Intrinsic<[],
433 [llvm_ptr_ty, llvm_anyvector_ty,
434 LLVMMatchType<0>, LLVMMatchType<0>,
435 llvm_i32_ty], [IntrReadWriteArgMem]>;
436 def int_arm_neon_vst4 : Intrinsic<[],
437 [llvm_ptr_ty, llvm_anyvector_ty,
438 LLVMMatchType<0>, LLVMMatchType<0>,
439 LLVMMatchType<0>, llvm_i32_ty],
440 [IntrReadWriteArgMem]>;
442 // Vector store N-element structure from one lane.
443 // Source operands are: the address, the N vectors, the lane number, and
445 def int_arm_neon_vst2lane : Intrinsic<[],
446 [llvm_ptr_ty, llvm_anyvector_ty,
447 LLVMMatchType<0>, llvm_i32_ty,
448 llvm_i32_ty], [IntrReadWriteArgMem]>;
449 def int_arm_neon_vst3lane : Intrinsic<[],
450 [llvm_ptr_ty, llvm_anyvector_ty,
451 LLVMMatchType<0>, LLVMMatchType<0>,
452 llvm_i32_ty, llvm_i32_ty],
453 [IntrReadWriteArgMem]>;
454 def int_arm_neon_vst4lane : Intrinsic<[],
455 [llvm_ptr_ty, llvm_anyvector_ty,
456 LLVMMatchType<0>, LLVMMatchType<0>,
457 LLVMMatchType<0>, llvm_i32_ty,
458 llvm_i32_ty], [IntrReadWriteArgMem]>;
460 // Vector bitwise select.
461 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
462 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
466 // Crypto instructions
467 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
468 [llvm_v16i8_ty], [IntrNoMem]>;
469 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
470 [llvm_v16i8_ty, llvm_v16i8_ty],
473 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
475 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
476 [llvm_v4i32_ty, llvm_v4i32_ty],
478 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
479 [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
481 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
482 [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
485 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
486 def int_arm_neon_aese : AES_2Arg_Intrinsic;
487 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
488 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
489 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
490 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
491 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
492 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
493 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
494 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
495 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
496 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
497 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
498 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
500 } // end TargetPrefix