include/llvm/IR/IntrinsicsARM64.td

   1 //===- IntrinsicsARM64.td - Defines ARM64 intrinsics -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM64-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let TargetPrefix = "arm64" in {
  15
  16 def int_arm64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
  17 def int_arm64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
  18 def int_arm64_clrex : Intrinsic<[]>;
  19
  20 def int_arm64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
  21 def int_arm64_stxp : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_i64_ty,
  22     llvm_ptr_ty]>;
  23
  24 def int_arm64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  25                                 LLVMMatchType<0>], [IntrNoMem]>;
  26 def int_arm64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  27                                 LLVMMatchType<0>], [IntrNoMem]>;
  28 }
  29
  30 //===----------------------------------------------------------------------===//
  31 // Advanced SIMD (NEON)
  32
  33 let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
  34   class AdvSIMD_2Scalar_Float_Intrinsic
  35     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  36                 [IntrNoMem]>;
  37
  38   class AdvSIMD_FPToIntRounding_Intrinsic
  39     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
  40
  41   class AdvSIMD_1IntArg_Intrinsic
  42     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  43   class AdvSIMD_1FloatArg_Intrinsic
  44     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  45   class AdvSIMD_1VectorArg_Intrinsic
  46     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  47   class AdvSIMD_1VectorArg_Expand_Intrinsic
  48     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  49   class AdvSIMD_1VectorArg_Long_Intrinsic
  50     : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
  51   class AdvSIMD_1IntArg_Narrow_Intrinsic
  52     : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
  53   class AdvSIMD_1VectorArg_Narrow_Intrinsic
  54     : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
  55   class AdvSIMD_1VectorArg_Int_Across_Intrinsic
  56     : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  57   class AdvSIMD_1VectorArg_Float_Across_Intrinsic
  58     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  59
  60   class AdvSIMD_2IntArg_Intrinsic
  61     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  62                 [IntrNoMem]>;
  63   class AdvSIMD_2FloatArg_Intrinsic
  64     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  65                 [IntrNoMem]>;
  66   class AdvSIMD_2VectorArg_Intrinsic
  67     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  68                 [IntrNoMem]>;
  69   class AdvSIMD_2VectorArg_Compare_Intrinsic
  70     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
  71                 [IntrNoMem]>;
  72   class AdvSIMD_2Arg_FloatCompare_Intrinsic
  73     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
  74                 [IntrNoMem]>;
  75   class AdvSIMD_2VectorArg_Long_Intrinsic
  76     : Intrinsic<[llvm_anyvector_ty],
  77                 [LLVMTruncatedType<0>,
  78                  LLVMTruncatedType<0>],
  79                 [IntrNoMem]>;
  80   class AdvSIMD_2VectorArg_Wide_Intrinsic
  81     : Intrinsic<[llvm_anyvector_ty],
  82                 [LLVMMatchType<0>, LLVMTruncatedType<0>],
  83                 [IntrNoMem]>;
  84   class AdvSIMD_2VectorArg_Narrow_Intrinsic
  85     : Intrinsic<[llvm_anyvector_ty],
  86                 [LLVMExtendedType<0>, LLVMExtendedType<0>],
  87                 [IntrNoMem]>;
  88   class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  89     : Intrinsic<[llvm_anyint_ty],
  90                 [LLVMExtendedType<0>, llvm_i32_ty],
  91                 [IntrNoMem]>;
  92   class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
  93     : Intrinsic<[llvm_anyvector_ty],
  94                 [llvm_anyvector_ty],
  95                 [IntrNoMem]>;
  96   class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
  97     : Intrinsic<[llvm_anyvector_ty],
  98                 [LLVMTruncatedType<0>],
  99                 [IntrNoMem]>;
 100   class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
 101     : Intrinsic<[llvm_anyvector_ty],
 102                 [LLVMTruncatedType<0>, llvm_i32_ty],
 103                 [IntrNoMem]>;
 104   class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
 105     : Intrinsic<[llvm_anyvector_ty],
 106                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
 107                 [IntrNoMem]>;
 108
 109   class AdvSIMD_3VectorArg_Intrinsic
 110       : Intrinsic<[llvm_anyvector_ty],
 111                [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 112                [IntrNoMem]>;
 113   class AdvSIMD_3VectorArg_Scalar_Intrinsic
 114       : Intrinsic<[llvm_anyvector_ty],
 115                [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
 116                [IntrNoMem]>;
 117   class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
 118       : Intrinsic<[llvm_anyvector_ty],
 119                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
 120                 LLVMMatchType<1>], [IntrNoMem]>;
 121   class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
 122     : Intrinsic<[llvm_anyvector_ty],
 123                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
 124                 [IntrNoMem]>;
 125   class AdvSIMD_CvtFxToFP_Intrinsic
 126     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
 127                 [IntrNoMem]>;
 128   class AdvSIMD_CvtFPToFx_Intrinsic
 129     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
 130                 [IntrNoMem]>;
 131 }
 132
 133 // Arithmetic ops
 134
 135 let Properties = [IntrNoMem] in {
 136   // Vector Add Across Lanes
 137   def int_arm64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 138   def int_arm64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 139   def int_arm64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 140
 141   // Vector Long Add Across Lanes
 142   def int_arm64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 143   def int_arm64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 144
 145   // Vector Halving Add
 146   def int_arm64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
 147   def int_arm64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
 148
 149   // Vector Rounding Halving Add
 150   def int_arm64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
 151   def int_arm64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
 152
 153   // Vector Saturating Add
 154   def int_arm64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
 155   def int_arm64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
 156   def int_arm64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
 157   def int_arm64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
 158
 159   // Vector Add High-Half
 160   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 161   // header is no longer supported.
 162   def int_arm64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 163
 164   // Vector Rounding Add High-Half
 165   def int_arm64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 166
 167   // Vector Saturating Doubling Multiply High
 168   def int_arm64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
 169
 170   // Vector Saturating Rounding Doubling Multiply High
 171   def int_arm64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
 172
 173   // Vector Polynominal Multiply
 174   def int_arm64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
 175
 176   // Vector Long Multiply
 177   def int_arm64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
 178   def int_arm64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
 179   def int_arm64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 180
 181   // Vector Extending Multiply
 182   def int_arm64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic;
 183
 184   // Vector Saturating Doubling Long Multiply
 185   def int_arm64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 186   def int_arm64_neon_sqdmulls_scalar
 187     : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 188
 189   // Vector Halving Subtract
 190   def int_arm64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
 191   def int_arm64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
 192
 193   // Vector Saturating Subtract
 194   def int_arm64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
 195   def int_arm64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
 196
 197   // Vector Subtract High-Half
 198   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 199   // header is no longer supported.
 200   def int_arm64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 201
 202   // Vector Rounding Subtract High-Half
 203   def int_arm64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 204
 205   // Vector Compare Absolute Greater-than-or-equal
 206   def int_arm64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 207
 208   // Vector Compare Absolute Greater-than
 209   def int_arm64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 210
 211   // Vector Absolute Difference
 212   def int_arm64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
 213   def int_arm64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
 214   def int_arm64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
 215
 216   // Scalar Absolute Difference
 217   def int_arm64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
 218
 219   // Vector Max
 220   def int_arm64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
 221   def int_arm64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
 222   def int_arm64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic;
 223   def int_arm64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
 224
 225   // Vector Max Across Lanes
 226   def int_arm64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 227   def int_arm64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 228   def int_arm64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 229   def int_arm64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 230
 231   // Vector Min
 232   def int_arm64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
 233   def int_arm64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
 234   def int_arm64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic;
 235   def int_arm64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
 236
 237   // Vector Min/Max Number
 238   def int_arm64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
 239   def int_arm64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
 240
 241   // Vector Min Across Lanes
 242   def int_arm64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 243   def int_arm64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 244   def int_arm64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 245   def int_arm64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 246
 247   // Pairwise Add
 248   def int_arm64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
 249
 250   // Long Pairwise Add
 251   // FIXME: In theory, we shouldn't need intrinsics for saddlp or
 252   // uaddlp, but tblgen's type inference currently can't handle the
 253   // pattern fragments this ends up generating.
 254   def int_arm64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 255   def int_arm64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 256
 257   // Folding Maximum
 258   def int_arm64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
 259   def int_arm64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
 260   def int_arm64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
 261
 262   // Folding Minimum
 263   def int_arm64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
 264   def int_arm64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
 265   def int_arm64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
 266
 267   // Reciprocal Estimate/Step
 268   def int_arm64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
 269   def int_arm64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
 270
 271   // Vector Saturating Shift Left
 272   def int_arm64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
 273   def int_arm64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
 274
 275   // Vector Rounding Shift Left
 276   def int_arm64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
 277   def int_arm64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
 278
 279   // Vector Saturating Rounding Shift Left
 280   def int_arm64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
 281   def int_arm64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
 282
 283   // Vector Signed->Unsigned Shift Left by Constant
 284   def int_arm64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
 285
 286   // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
 287   def int_arm64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 288
 289   // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
 290   def int_arm64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 291
 292   // Vector Narrowing Shift Right by Constant
 293   def int_arm64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 294   def int_arm64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 295
 296   // Vector Rounding Narrowing Shift Right by Constant
 297   def int_arm64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 298
 299   // Vector Rounding Narrowing Saturating Shift Right by Constant
 300   def int_arm64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 301   def int_arm64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 302
 303   // Vector Shift Left
 304   def int_arm64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
 305   def int_arm64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
 306
 307   // Vector Widening Shift Left by Constant
 308   def int_arm64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
 309   def int_arm64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 310   def int_arm64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 311
 312   // Vector Shift Right by Constant and Insert
 313   def int_arm64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 314
 315   // Vector Shift Left by Constant and Insert
 316   def int_arm64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 317
 318   // Vector Saturating Narrow
 319   def int_arm64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
 320   def int_arm64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
 321   def int_arm64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 322   def int_arm64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 323
 324   // Vector Saturating Extract and Unsigned Narrow
 325   def int_arm64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
 326   def int_arm64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 327
 328   // Vector Absolute Value
 329   def int_arm64_neon_abs : AdvSIMD_1VectorArg_Intrinsic;
 330
 331   // Vector Saturating Absolute Value
 332   def int_arm64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
 333
 334   // Vector Saturating Negation
 335   def int_arm64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
 336
 337   // Vector Count Leading Sign Bits
 338   def int_arm64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
 339
 340   // Vector Reciprocal Estimate
 341   def int_arm64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
 342   def int_arm64_neon_frecpe : AdvSIMD_1VectorArg_Intrinsic;
 343
 344   // Vector Square Root Estimate
 345   def int_arm64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
 346   def int_arm64_neon_frsqrte : AdvSIMD_1VectorArg_Intrinsic;
 347
 348   // Vector Bitwise Reverse
 349   def int_arm64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
 350
 351   // Vector Conversions Between Half-Precision and Single-Precision.
 352   def int_arm64_neon_vcvtfp2hf
 353     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 354   def int_arm64_neon_vcvthf2fp
 355     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 356
 357   // Vector Conversions Between Floating-point and Fixed-point.
 358   def int_arm64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
 359   def int_arm64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
 360   def int_arm64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 361   def int_arm64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 362
 363   // Vector FP->Int Conversions
 364   def int_arm64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
 365   def int_arm64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
 366   def int_arm64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
 367   def int_arm64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
 368   def int_arm64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
 369   def int_arm64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
 370   def int_arm64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
 371   def int_arm64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
 372   def int_arm64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
 373   def int_arm64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
 374
 375   // Vector FP Rounding: only ties to even is unrepresented by a normal
 376   // intrinsic.
 377   def int_arm64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
 378
 379   // Scalar FP->Int conversions
 380
 381   // Vector FP Inexact Narrowing
 382   def int_arm64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
 383
 384   // Scalar FP Inexact Narrowing
 385   def int_arm64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
 386                                         [IntrNoMem]>;
 387 }
 388
 389 let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
 390   class AdvSIMD_2Vector2Index_Intrinsic
 391     : Intrinsic<[llvm_anyvector_ty],
 392                 [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
 393                 [IntrNoMem]>;
 394 }
 395
 396 // Vector element to element moves
 397 def int_arm64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
 398
 399 let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
 400   class AdvSIMD_1Vec_Load_Intrinsic
 401       : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
 402                   [IntrReadArgMem]>;
 403   class AdvSIMD_1Vec_Store_Lane_Intrinsic
 404     : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
 405                 [IntrReadWriteArgMem, NoCapture<2>]>;
 406
 407   class AdvSIMD_2Vec_Load_Intrinsic
 408     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 409                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 410                 [IntrReadArgMem]>;
 411   class AdvSIMD_2Vec_Load_Lane_Intrinsic
 412     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 413                 [LLVMMatchType<0>, LLVMMatchType<0>,
 414                  llvm_i64_ty, llvm_anyptr_ty],
 415                 [IntrReadArgMem]>;
 416   class AdvSIMD_2Vec_Store_Intrinsic
 417     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 418                      LLVMAnyPointerType<LLVMMatchType<0>>],
 419                 [IntrReadWriteArgMem, NoCapture<2>]>;
 420   class AdvSIMD_2Vec_Store_Lane_Intrinsic
 421     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 422                  llvm_i64_ty, llvm_anyptr_ty],
 423                 [IntrReadWriteArgMem, NoCapture<3>]>;
 424
 425   class AdvSIMD_3Vec_Load_Intrinsic
 426     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 427                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 428                 [IntrReadArgMem]>;
 429   class AdvSIMD_3Vec_Load_Lane_Intrinsic
 430     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 431                 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
 432                  llvm_i64_ty, llvm_anyptr_ty],
 433                 [IntrReadArgMem]>;
 434   class AdvSIMD_3Vec_Store_Intrinsic
 435     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 436                      LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
 437                 [IntrReadWriteArgMem, NoCapture<3>]>;
 438   class AdvSIMD_3Vec_Store_Lane_Intrinsic
 439     : Intrinsic<[], [llvm_anyvector_ty,
 440                  LLVMMatchType<0>, LLVMMatchType<0>,
 441                  llvm_i64_ty, llvm_anyptr_ty],
 442                 [IntrReadWriteArgMem, NoCapture<4>]>;
 443
 444   class AdvSIMD_4Vec_Load_Intrinsic
 445     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 446                  LLVMMatchType<0>, LLVMMatchType<0>],
 447                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 448                 [IntrReadArgMem]>;
 449   class AdvSIMD_4Vec_Load_Lane_Intrinsic
 450     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 451                  LLVMMatchType<0>, LLVMMatchType<0>],
 452                 [LLVMMatchType<0>, LLVMMatchType<0>,
 453                  LLVMMatchType<0>, LLVMMatchType<0>,
 454                  llvm_i64_ty, llvm_anyptr_ty],
 455                 [IntrReadArgMem]>;
 456   class AdvSIMD_4Vec_Store_Intrinsic
 457     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 458                  LLVMMatchType<0>, LLVMMatchType<0>,
 459                  LLVMAnyPointerType<LLVMMatchType<0>>],
 460                 [IntrReadWriteArgMem, NoCapture<4>]>;
 461   class AdvSIMD_4Vec_Store_Lane_Intrinsic
 462     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 463                  LLVMMatchType<0>, LLVMMatchType<0>,
 464                  llvm_i64_ty, llvm_anyptr_ty],
 465                 [IntrReadWriteArgMem, NoCapture<5>]>;
 466 }
 467
 468 // Memory ops
 469
 470 def int_arm64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
 471 def int_arm64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
 472 def int_arm64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
 473
 474 def int_arm64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
 475 def int_arm64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
 476 def int_arm64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
 477
 478 def int_arm64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
 479 def int_arm64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
 480 def int_arm64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
 481
 482 def int_arm64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
 483 def int_arm64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
 484 def int_arm64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
 485
 486 def int_arm64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
 487 def int_arm64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
 488 def int_arm64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
 489
 490 def int_arm64_neon_st2  : AdvSIMD_2Vec_Store_Intrinsic;
 491 def int_arm64_neon_st3  : AdvSIMD_3Vec_Store_Intrinsic;
 492 def int_arm64_neon_st4  : AdvSIMD_4Vec_Store_Intrinsic;
 493
 494 def int_arm64_neon_st2lane  : AdvSIMD_2Vec_Store_Lane_Intrinsic;
 495 def int_arm64_neon_st3lane  : AdvSIMD_3Vec_Store_Lane_Intrinsic;
 496 def int_arm64_neon_st4lane  : AdvSIMD_4Vec_Store_Lane_Intrinsic;
 497
 498 let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
 499   class AdvSIMD_Tbl1_Intrinsic
 500     : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
 501                 [IntrNoMem]>;
 502   class AdvSIMD_Tbl2_Intrinsic
 503     : Intrinsic<[llvm_anyvector_ty],
 504                 [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
 505   class AdvSIMD_Tbl3_Intrinsic
 506     : Intrinsic<[llvm_anyvector_ty],
 507                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 508                  LLVMMatchType<0>],
 509                 [IntrNoMem]>;
 510   class AdvSIMD_Tbl4_Intrinsic
 511     : Intrinsic<[llvm_anyvector_ty],
 512                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 513                  LLVMMatchType<0>],
 514                 [IntrNoMem]>;
 515
 516   class AdvSIMD_Tbx1_Intrinsic
 517     : Intrinsic<[llvm_anyvector_ty],
 518                 [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
 519                 [IntrNoMem]>;
 520   class AdvSIMD_Tbx2_Intrinsic
 521     : Intrinsic<[llvm_anyvector_ty],
 522                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 523                  LLVMMatchType<0>],
 524                 [IntrNoMem]>;
 525   class AdvSIMD_Tbx3_Intrinsic
 526     : Intrinsic<[llvm_anyvector_ty],
 527                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 528                  llvm_v16i8_ty, LLVMMatchType<0>],
 529                 [IntrNoMem]>;
 530   class AdvSIMD_Tbx4_Intrinsic
 531     : Intrinsic<[llvm_anyvector_ty],
 532                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 533                  llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
 534                 [IntrNoMem]>;
 535 }
 536 def int_arm64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
 537 def int_arm64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
 538 def int_arm64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
 539 def int_arm64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
 540
 541 def int_arm64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
 542 def int_arm64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
 543 def int_arm64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
 544 def int_arm64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
 545
 546 let TargetPrefix = "arm64" in {
 547   class Crypto_AES_DataKey_Intrinsic
 548     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
 549
 550   class Crypto_AES_Data_Intrinsic
 551     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
 552
 553   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 554   // (v4i32).
 555   class Crypto_SHA_5Hash4Schedule_Intrinsic
 556     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 557                 [IntrNoMem]>;
 558
 559   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 560   // (v4i32).
 561   class Crypto_SHA_1Hash_Intrinsic
 562     : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 563
 564   // SHA intrinsic taking 8 words of the schedule
 565   class Crypto_SHA_8Schedule_Intrinsic
 566     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
 567
 568   // SHA intrinsic taking 12 words of the schedule
 569   class Crypto_SHA_12Schedule_Intrinsic
 570     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 571                 [IntrNoMem]>;
 572
 573   // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
 574   class Crypto_SHA_8Hash4Schedule_Intrinsic
 575     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 576                 [IntrNoMem]>;
 577 }
 578
 579 // AES
 580 def int_arm64_crypto_aese   : Crypto_AES_DataKey_Intrinsic;
 581 def int_arm64_crypto_aesd   : Crypto_AES_DataKey_Intrinsic;
 582 def int_arm64_crypto_aesmc  : Crypto_AES_Data_Intrinsic;
 583 def int_arm64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
 584
 585 // SHA1
 586 def int_arm64_crypto_sha1c  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 587 def int_arm64_crypto_sha1p  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 588 def int_arm64_crypto_sha1m  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 589 def int_arm64_crypto_sha1h  : Crypto_SHA_1Hash_Intrinsic;
 590
 591 def int_arm64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
 592 def int_arm64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
 593
 594 // SHA256
 595 def int_arm64_crypto_sha256h   : Crypto_SHA_8Hash4Schedule_Intrinsic;
 596 def int_arm64_crypto_sha256h2  : Crypto_SHA_8Hash4Schedule_Intrinsic;
 597 def int_arm64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
 598 def int_arm64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
 599
 600 //===----------------------------------------------------------------------===//
 601 // CRC32
 602
 603 let TargetPrefix = "arm64" in {
 604
 605 def int_arm64_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 606     [IntrNoMem]>;
 607 def int_arm64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 608     [IntrNoMem]>;
 609 def int_arm64_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 610     [IntrNoMem]>;
 611 def int_arm64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 612     [IntrNoMem]>;
 613 def int_arm64_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 614     [IntrNoMem]>;
 615 def int_arm64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 616     [IntrNoMem]>;
 617 def int_arm64_crc32x  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 618     [IntrNoMem]>;
 619 def int_arm64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 620     [IntrNoMem]>;
 621 }