include/llvm/IR/IntrinsicsARM64.td

   1 //===- IntrinsicsARM64.td - Defines ARM64 intrinsics -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM64-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let TargetPrefix = "arm64" in {
  15
  16 def int_arm64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
  17 def int_arm64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
  18 def int_arm64_clrex : Intrinsic<[]>;
  19
  20 def int_arm64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
  21 def int_arm64_stxp : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_i64_ty,
  22     llvm_ptr_ty]>;
  23
  24 def int_arm64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  25                                 LLVMMatchType<0>], [IntrNoMem]>;
  26 def int_arm64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  27                                 LLVMMatchType<0>], [IntrNoMem]>;
  28 }
  29
  30 //===----------------------------------------------------------------------===//
  31 // Advanced SIMD (NEON)
  32
  33 let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
  34   class AdvSIMD_2Scalar_Float_Intrinsic
  35     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  36                 [IntrNoMem]>;
  37
  38   class AdvSIMD_FPToIntRounding_Intrinsic
  39     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
  40
  41   class AdvSIMD_1IntArg_Intrinsic
  42     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  43   class AdvSIMD_1FloatArg_Intrinsic
  44     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  45   class AdvSIMD_1VectorArg_Intrinsic
  46     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  47   class AdvSIMD_1VectorArg_Expand_Intrinsic
  48     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  49   class AdvSIMD_1VectorArg_Long_Intrinsic
  50     : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
  51   class AdvSIMD_1IntArg_Narrow_Intrinsic
  52     : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
  53   class AdvSIMD_1VectorArg_Narrow_Intrinsic
  54     : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
  55   class AdvSIMD_1VectorArg_Int_Across_Intrinsic
  56     : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  57   class AdvSIMD_1VectorArg_Float_Across_Intrinsic
  58     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  59
  60   class AdvSIMD_2IntArg_Intrinsic
  61     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  62                 [IntrNoMem]>;
  63   class AdvSIMD_2FloatArg_Intrinsic
  64     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  65                 [IntrNoMem]>;
  66   class AdvSIMD_2VectorArg_Intrinsic
  67     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  68                 [IntrNoMem]>;
  69   class AdvSIMD_2VectorArg_Compare_Intrinsic
  70     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
  71                 [IntrNoMem]>;
  72   class AdvSIMD_2Arg_FloatCompare_Intrinsic
  73     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
  74                 [IntrNoMem]>;
  75   class AdvSIMD_2VectorArg_Long_Intrinsic
  76     : Intrinsic<[llvm_anyvector_ty],
  77                 [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
  78                 [IntrNoMem]>;
  79   class AdvSIMD_2VectorArg_Wide_Intrinsic
  80     : Intrinsic<[llvm_anyvector_ty],
  81                 [LLVMMatchType<0>, LLVMTruncatedType<0>],
  82                 [IntrNoMem]>;
  83   class AdvSIMD_2VectorArg_Narrow_Intrinsic
  84     : Intrinsic<[llvm_anyvector_ty],
  85                 [LLVMExtendedType<0>, LLVMExtendedType<0>],
  86                 [IntrNoMem]>;
  87   class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
  88     : Intrinsic<[llvm_anyint_ty],
  89                 [LLVMExtendedType<0>, llvm_i32_ty],
  90                 [IntrNoMem]>;
  91   class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
  92     : Intrinsic<[llvm_anyvector_ty],
  93                 [llvm_anyvector_ty],
  94                 [IntrNoMem]>;
  95   class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
  96     : Intrinsic<[llvm_anyvector_ty],
  97                 [LLVMTruncatedType<0>],
  98                 [IntrNoMem]>;
  99   class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
 100     : Intrinsic<[llvm_anyvector_ty],
 101                 [LLVMTruncatedType<0>, llvm_i32_ty],
 102                 [IntrNoMem]>;
 103   class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
 104     : Intrinsic<[llvm_anyvector_ty],
 105                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
 106                 [IntrNoMem]>;
 107
 108   class AdvSIMD_3VectorArg_Intrinsic
 109       : Intrinsic<[llvm_anyvector_ty],
 110                [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 111                [IntrNoMem]>;
 112   class AdvSIMD_3VectorArg_Scalar_Intrinsic
 113       : Intrinsic<[llvm_anyvector_ty],
 114                [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
 115                [IntrNoMem]>;
 116   class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
 117       : Intrinsic<[llvm_anyvector_ty],
 118                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
 119                 LLVMMatchType<1>], [IntrNoMem]>;
 120   class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
 121     : Intrinsic<[llvm_anyvector_ty],
 122                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
 123                 [IntrNoMem]>;
 124   class AdvSIMD_CvtFxToFP_Intrinsic
 125     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
 126                 [IntrNoMem]>;
 127   class AdvSIMD_CvtFPToFx_Intrinsic
 128     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
 129                 [IntrNoMem]>;
 130 }
 131
 132 // Arithmetic ops
 133
 134 let Properties = [IntrNoMem] in {
 135   // Vector Add Across Lanes
 136   def int_arm64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 137   def int_arm64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 138   def int_arm64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 139
 140   // Vector Long Add Across Lanes
 141   def int_arm64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 142   def int_arm64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 143
 144   // Vector Halving Add
 145   def int_arm64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
 146   def int_arm64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
 147
 148   // Vector Rounding Halving Add
 149   def int_arm64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
 150   def int_arm64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
 151
 152   // Vector Saturating Add
 153   def int_arm64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
 154   def int_arm64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
 155   def int_arm64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
 156   def int_arm64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
 157
 158   // Vector Add High-Half
 159   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 160   // header is no longer supported.
 161   def int_arm64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 162
 163   // Vector Rounding Add High-Half
 164   def int_arm64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 165
 166   // Vector Saturating Doubling Multiply High
 167   def int_arm64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
 168
 169   // Vector Saturating Rounding Doubling Multiply High
 170   def int_arm64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
 171
 172   // Vector Polynominal Multiply
 173   def int_arm64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
 174
 175   // Vector Long Multiply
 176   def int_arm64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
 177   def int_arm64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
 178   def int_arm64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 179
 180   // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
 181   // it with a v16i8.
 182   def int_arm64_neon_pmull64 :
 183         Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
 184
 185   // Vector Extending Multiply
 186   def int_arm64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic;
 187
 188   // Vector Saturating Doubling Long Multiply
 189   def int_arm64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 190   def int_arm64_neon_sqdmulls_scalar
 191     : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 192
 193   // Vector Halving Subtract
 194   def int_arm64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
 195   def int_arm64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
 196
 197   // Vector Saturating Subtract
 198   def int_arm64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
 199   def int_arm64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
 200
 201   // Vector Subtract High-Half
 202   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 203   // header is no longer supported.
 204   def int_arm64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 205
 206   // Vector Rounding Subtract High-Half
 207   def int_arm64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 208
 209   // Vector Compare Absolute Greater-than-or-equal
 210   def int_arm64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 211
 212   // Vector Compare Absolute Greater-than
 213   def int_arm64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 214
 215   // Vector Absolute Difference
 216   def int_arm64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
 217   def int_arm64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
 218   def int_arm64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
 219
 220   // Scalar Absolute Difference
 221   def int_arm64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
 222
 223   // Vector Max
 224   def int_arm64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
 225   def int_arm64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
 226   def int_arm64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic;
 227   def int_arm64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
 228
 229   // Vector Max Across Lanes
 230   def int_arm64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 231   def int_arm64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 232   def int_arm64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 233   def int_arm64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 234
 235   // Vector Min
 236   def int_arm64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
 237   def int_arm64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
 238   def int_arm64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic;
 239   def int_arm64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
 240
 241   // Vector Min/Max Number
 242   def int_arm64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
 243   def int_arm64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
 244
 245   // Vector Min Across Lanes
 246   def int_arm64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 247   def int_arm64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 248   def int_arm64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 249   def int_arm64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 250
 251   // Pairwise Add
 252   def int_arm64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
 253
 254   // Long Pairwise Add
 255   // FIXME: In theory, we shouldn't need intrinsics for saddlp or
 256   // uaddlp, but tblgen's type inference currently can't handle the
 257   // pattern fragments this ends up generating.
 258   def int_arm64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 259   def int_arm64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 260
 261   // Folding Maximum
 262   def int_arm64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
 263   def int_arm64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
 264   def int_arm64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
 265
 266   // Folding Minimum
 267   def int_arm64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
 268   def int_arm64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
 269   def int_arm64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
 270
 271   // Reciprocal Estimate/Step
 272   def int_arm64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
 273   def int_arm64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
 274
 275   // Reciprocal Exponent
 276   def int_arm64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic;
 277
 278   // Vector Saturating Shift Left
 279   def int_arm64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
 280   def int_arm64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
 281
 282   // Vector Rounding Shift Left
 283   def int_arm64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
 284   def int_arm64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
 285
 286   // Vector Saturating Rounding Shift Left
 287   def int_arm64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
 288   def int_arm64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
 289
 290   // Vector Signed->Unsigned Shift Left by Constant
 291   def int_arm64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
 292
 293   // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
 294   def int_arm64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 295
 296   // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
 297   def int_arm64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 298
 299   // Vector Narrowing Shift Right by Constant
 300   def int_arm64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 301   def int_arm64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 302
 303   // Vector Rounding Narrowing Shift Right by Constant
 304   def int_arm64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 305
 306   // Vector Rounding Narrowing Saturating Shift Right by Constant
 307   def int_arm64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 308   def int_arm64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 309
 310   // Vector Shift Left
 311   def int_arm64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
 312   def int_arm64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
 313
 314   // Vector Widening Shift Left by Constant
 315   def int_arm64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
 316   def int_arm64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 317   def int_arm64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 318
 319   // Vector Shift Right by Constant and Insert
 320   def int_arm64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 321
 322   // Vector Shift Left by Constant and Insert
 323   def int_arm64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 324
 325   // Vector Saturating Narrow
 326   def int_arm64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
 327   def int_arm64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
 328   def int_arm64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 329   def int_arm64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 330
 331   // Vector Saturating Extract and Unsigned Narrow
 332   def int_arm64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
 333   def int_arm64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 334
 335   // Vector Absolute Value
 336   def int_arm64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
 337
 338   // Vector Saturating Absolute Value
 339   def int_arm64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
 340
 341   // Vector Saturating Negation
 342   def int_arm64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
 343
 344   // Vector Count Leading Sign Bits
 345   def int_arm64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
 346
 347   // Vector Reciprocal Estimate
 348   def int_arm64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
 349   def int_arm64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic;
 350
 351   // Vector Square Root Estimate
 352   def int_arm64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
 353   def int_arm64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic;
 354
 355   // Vector Bitwise Reverse
 356   def int_arm64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
 357
 358   // Vector Conversions Between Half-Precision and Single-Precision.
 359   def int_arm64_neon_vcvtfp2hf
 360     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 361   def int_arm64_neon_vcvthf2fp
 362     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 363
 364   // Vector Conversions Between Floating-point and Fixed-point.
 365   def int_arm64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
 366   def int_arm64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
 367   def int_arm64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 368   def int_arm64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 369
 370   // Vector FP->Int Conversions
 371   def int_arm64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
 372   def int_arm64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
 373   def int_arm64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
 374   def int_arm64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
 375   def int_arm64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
 376   def int_arm64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
 377   def int_arm64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
 378   def int_arm64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
 379   def int_arm64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
 380   def int_arm64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
 381
 382   // Vector FP Rounding: only ties to even is unrepresented by a normal
 383   // intrinsic.
 384   def int_arm64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
 385
 386   // Scalar FP->Int conversions
 387
 388   // Vector FP Inexact Narrowing
 389   def int_arm64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
 390
 391   // Scalar FP Inexact Narrowing
 392   def int_arm64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
 393                                         [IntrNoMem]>;
 394 }
 395
 396 let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
 397   class AdvSIMD_2Vector2Index_Intrinsic
 398     : Intrinsic<[llvm_anyvector_ty],
 399                 [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
 400                 [IntrNoMem]>;
 401 }
 402
 403 // Vector element to element moves
 404 def int_arm64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
 405
 406 let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
 407   class AdvSIMD_1Vec_Load_Intrinsic
 408       : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
 409                   [IntrReadArgMem]>;
 410   class AdvSIMD_1Vec_Store_Lane_Intrinsic
 411     : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
 412                 [IntrReadWriteArgMem, NoCapture<2>]>;
 413
 414   class AdvSIMD_2Vec_Load_Intrinsic
 415     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 416                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 417                 [IntrReadArgMem]>;
 418   class AdvSIMD_2Vec_Load_Lane_Intrinsic
 419     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 420                 [LLVMMatchType<0>, LLVMMatchType<0>,
 421                  llvm_i64_ty, llvm_anyptr_ty],
 422                 [IntrReadArgMem]>;
 423   class AdvSIMD_2Vec_Store_Intrinsic
 424     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 425                      LLVMAnyPointerType<LLVMMatchType<0>>],
 426                 [IntrReadWriteArgMem, NoCapture<2>]>;
 427   class AdvSIMD_2Vec_Store_Lane_Intrinsic
 428     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 429                  llvm_i64_ty, llvm_anyptr_ty],
 430                 [IntrReadWriteArgMem, NoCapture<3>]>;
 431
 432   class AdvSIMD_3Vec_Load_Intrinsic
 433     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 434                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 435                 [IntrReadArgMem]>;
 436   class AdvSIMD_3Vec_Load_Lane_Intrinsic
 437     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 438                 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
 439                  llvm_i64_ty, llvm_anyptr_ty],
 440                 [IntrReadArgMem]>;
 441   class AdvSIMD_3Vec_Store_Intrinsic
 442     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 443                      LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
 444                 [IntrReadWriteArgMem, NoCapture<3>]>;
 445   class AdvSIMD_3Vec_Store_Lane_Intrinsic
 446     : Intrinsic<[], [llvm_anyvector_ty,
 447                  LLVMMatchType<0>, LLVMMatchType<0>,
 448                  llvm_i64_ty, llvm_anyptr_ty],
 449                 [IntrReadWriteArgMem, NoCapture<4>]>;
 450
 451   class AdvSIMD_4Vec_Load_Intrinsic
 452     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 453                  LLVMMatchType<0>, LLVMMatchType<0>],
 454                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 455                 [IntrReadArgMem]>;
 456   class AdvSIMD_4Vec_Load_Lane_Intrinsic
 457     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 458                  LLVMMatchType<0>, LLVMMatchType<0>],
 459                 [LLVMMatchType<0>, LLVMMatchType<0>,
 460                  LLVMMatchType<0>, LLVMMatchType<0>,
 461                  llvm_i64_ty, llvm_anyptr_ty],
 462                 [IntrReadArgMem]>;
 463   class AdvSIMD_4Vec_Store_Intrinsic
 464     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 465                  LLVMMatchType<0>, LLVMMatchType<0>,
 466                  LLVMAnyPointerType<LLVMMatchType<0>>],
 467                 [IntrReadWriteArgMem, NoCapture<4>]>;
 468   class AdvSIMD_4Vec_Store_Lane_Intrinsic
 469     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 470                  LLVMMatchType<0>, LLVMMatchType<0>,
 471                  llvm_i64_ty, llvm_anyptr_ty],
 472                 [IntrReadWriteArgMem, NoCapture<5>]>;
 473 }
 474
 475 // Memory ops
 476
 477 def int_arm64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
 478 def int_arm64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
 479 def int_arm64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
 480
 481 def int_arm64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
 482 def int_arm64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
 483 def int_arm64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
 484
 485 def int_arm64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
 486 def int_arm64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
 487 def int_arm64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
 488
 489 def int_arm64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
 490 def int_arm64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
 491 def int_arm64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
 492
 493 def int_arm64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
 494 def int_arm64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
 495 def int_arm64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
 496
 497 def int_arm64_neon_st2  : AdvSIMD_2Vec_Store_Intrinsic;
 498 def int_arm64_neon_st3  : AdvSIMD_3Vec_Store_Intrinsic;
 499 def int_arm64_neon_st4  : AdvSIMD_4Vec_Store_Intrinsic;
 500
 501 def int_arm64_neon_st2lane  : AdvSIMD_2Vec_Store_Lane_Intrinsic;
 502 def int_arm64_neon_st3lane  : AdvSIMD_3Vec_Store_Lane_Intrinsic;
 503 def int_arm64_neon_st4lane  : AdvSIMD_4Vec_Store_Lane_Intrinsic;
 504
 505 let TargetPrefix = "arm64" in {  // All intrinsics start with "llvm.arm64.".
 506   class AdvSIMD_Tbl1_Intrinsic
 507     : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
 508                 [IntrNoMem]>;
 509   class AdvSIMD_Tbl2_Intrinsic
 510     : Intrinsic<[llvm_anyvector_ty],
 511                 [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
 512   class AdvSIMD_Tbl3_Intrinsic
 513     : Intrinsic<[llvm_anyvector_ty],
 514                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 515                  LLVMMatchType<0>],
 516                 [IntrNoMem]>;
 517   class AdvSIMD_Tbl4_Intrinsic
 518     : Intrinsic<[llvm_anyvector_ty],
 519                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 520                  LLVMMatchType<0>],
 521                 [IntrNoMem]>;
 522
 523   class AdvSIMD_Tbx1_Intrinsic
 524     : Intrinsic<[llvm_anyvector_ty],
 525                 [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
 526                 [IntrNoMem]>;
 527   class AdvSIMD_Tbx2_Intrinsic
 528     : Intrinsic<[llvm_anyvector_ty],
 529                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 530                  LLVMMatchType<0>],
 531                 [IntrNoMem]>;
 532   class AdvSIMD_Tbx3_Intrinsic
 533     : Intrinsic<[llvm_anyvector_ty],
 534                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 535                  llvm_v16i8_ty, LLVMMatchType<0>],
 536                 [IntrNoMem]>;
 537   class AdvSIMD_Tbx4_Intrinsic
 538     : Intrinsic<[llvm_anyvector_ty],
 539                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 540                  llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
 541                 [IntrNoMem]>;
 542 }
 543 def int_arm64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
 544 def int_arm64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
 545 def int_arm64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
 546 def int_arm64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
 547
 548 def int_arm64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
 549 def int_arm64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
 550 def int_arm64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
 551 def int_arm64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
 552
 553 let TargetPrefix = "arm64" in {
 554   class Crypto_AES_DataKey_Intrinsic
 555     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
 556
 557   class Crypto_AES_Data_Intrinsic
 558     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
 559
 560   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 561   // (v4i32).
 562   class Crypto_SHA_5Hash4Schedule_Intrinsic
 563     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 564                 [IntrNoMem]>;
 565
 566   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 567   // (v4i32).
 568   class Crypto_SHA_1Hash_Intrinsic
 569     : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 570
 571   // SHA intrinsic taking 8 words of the schedule
 572   class Crypto_SHA_8Schedule_Intrinsic
 573     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
 574
 575   // SHA intrinsic taking 12 words of the schedule
 576   class Crypto_SHA_12Schedule_Intrinsic
 577     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 578                 [IntrNoMem]>;
 579
 580   // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
 581   class Crypto_SHA_8Hash4Schedule_Intrinsic
 582     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 583                 [IntrNoMem]>;
 584 }
 585
 586 // AES
 587 def int_arm64_crypto_aese   : Crypto_AES_DataKey_Intrinsic;
 588 def int_arm64_crypto_aesd   : Crypto_AES_DataKey_Intrinsic;
 589 def int_arm64_crypto_aesmc  : Crypto_AES_Data_Intrinsic;
 590 def int_arm64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
 591
 592 // SHA1
 593 def int_arm64_crypto_sha1c  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 594 def int_arm64_crypto_sha1p  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 595 def int_arm64_crypto_sha1m  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 596 def int_arm64_crypto_sha1h  : Crypto_SHA_1Hash_Intrinsic;
 597
 598 def int_arm64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
 599 def int_arm64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
 600
 601 // SHA256
 602 def int_arm64_crypto_sha256h   : Crypto_SHA_8Hash4Schedule_Intrinsic;
 603 def int_arm64_crypto_sha256h2  : Crypto_SHA_8Hash4Schedule_Intrinsic;
 604 def int_arm64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
 605 def int_arm64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
 606
 607 //===----------------------------------------------------------------------===//
 608 // CRC32
 609
 610 let TargetPrefix = "arm64" in {
 611
 612 def int_arm64_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 613     [IntrNoMem]>;
 614 def int_arm64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 615     [IntrNoMem]>;
 616 def int_arm64_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 617     [IntrNoMem]>;
 618 def int_arm64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 619     [IntrNoMem]>;
 620 def int_arm64_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 621     [IntrNoMem]>;
 622 def int_arm64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 623     [IntrNoMem]>;
 624 def int_arm64_crc32x  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 625     [IntrNoMem]>;
 626 def int_arm64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 627     [IntrNoMem]>;
 628 }