1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
27 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
28 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
29 [IntrNoMem, Commutative]>;
30 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
31 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
32 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
33 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
34 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
35 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
38 //===----------------------------------------------------------------------===//
41 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
42 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
43 Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
44 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
45 Intrinsic<[], [llvm_i32_ty], [IntrWriteMem]>;
46 def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
48 def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
52 //===----------------------------------------------------------------------===//
53 // Advanced SIMD (NEON)
55 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
57 // The following classes do not correspond directly to GCC builtins.
58 class Neon_1Arg_Intrinsic
59 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
60 class Neon_1Arg_Narrow_Intrinsic
61 : Intrinsic<[llvm_anyvector_ty],
62 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
63 class Neon_1Arg_Long_Intrinsic
64 : Intrinsic<[llvm_anyvector_ty],
65 [LLVMTruncatedElementVectorType<0>], [IntrNoMem]>;
66 class Neon_2Arg_Intrinsic
67 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
69 class Neon_2Arg_Narrow_Intrinsic
70 : Intrinsic<[llvm_anyvector_ty],
71 [LLVMExtendedElementVectorType<0>,
72 LLVMExtendedElementVectorType<0>],
74 class Neon_2Arg_Long_Intrinsic
75 : Intrinsic<[llvm_anyvector_ty],
76 [LLVMTruncatedElementVectorType<0>,
77 LLVMTruncatedElementVectorType<0>],
79 class Neon_2Arg_Wide_Intrinsic
80 : Intrinsic<[llvm_anyvector_ty],
81 [LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
83 class Neon_3Arg_Intrinsic
84 : Intrinsic<[llvm_anyvector_ty],
85 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
87 class Neon_3Arg_Long_Intrinsic
88 : Intrinsic<[llvm_anyvector_ty],
90 LLVMTruncatedElementVectorType<0>,
91 LLVMTruncatedElementVectorType<0>],
93 class Neon_CvtFxToFP_Intrinsic
94 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
95 class Neon_CvtFPToFx_Intrinsic
96 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
98 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
99 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
100 // Overall, the classes range from 2 to 6 v8i8 arguments.
101 class Neon_Tbl2Arg_Intrinsic
102 : Intrinsic<[llvm_v8i8_ty],
103 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
104 class Neon_Tbl3Arg_Intrinsic
105 : Intrinsic<[llvm_v8i8_ty],
106 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
107 class Neon_Tbl4Arg_Intrinsic
108 : Intrinsic<[llvm_v8i8_ty],
109 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
111 class Neon_Tbl5Arg_Intrinsic
112 : Intrinsic<[llvm_v8i8_ty],
113 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
114 llvm_v8i8_ty], [IntrNoMem]>;
115 class Neon_Tbl6Arg_Intrinsic
116 : Intrinsic<[llvm_v8i8_ty],
117 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
118 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
123 let Properties = [IntrNoMem, Commutative] in {
126 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
127 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
128 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
129 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
130 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
131 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
132 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
133 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
134 def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic;
135 def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic;
136 def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic;
137 def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic;
140 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
141 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
142 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
143 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
144 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
145 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
146 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
148 // Vector Multiply and Accumulate/Subtract.
149 def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic;
150 def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic;
151 def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic;
152 def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic;
153 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
154 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
157 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
158 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
161 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
162 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
164 // Vector Reciprocal Step.
165 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
167 // Vector Reciprocal Square Root Step.
168 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
172 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
173 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
174 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
175 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
176 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
177 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
178 def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic;
179 def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic;
180 def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic;
181 def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic;
183 // Vector Absolute Compare.
184 let TargetPrefix = "arm" in {
185 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
186 [llvm_v2f32_ty, llvm_v2f32_ty],
188 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
189 [llvm_v4f32_ty, llvm_v4f32_ty],
191 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
192 [llvm_v2f32_ty, llvm_v2f32_ty],
194 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
195 [llvm_v4f32_ty, llvm_v4f32_ty],
199 // Vector Absolute Differences.
200 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
201 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
202 def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic;
203 def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic;
205 // Vector Absolute Difference and Accumulate.
206 def int_arm_neon_vabas : Neon_3Arg_Intrinsic;
207 def int_arm_neon_vabau : Neon_3Arg_Intrinsic;
208 def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic;
209 def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic;
211 // Vector Pairwise Add.
212 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
214 // Vector Pairwise Add Long.
215 // Note: This is different than the other "long" NEON intrinsics because
216 // the result vector has half as many elements as the source vector.
217 // The source and destination vector types must be specified separately.
218 let TargetPrefix = "arm" in {
219 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
221 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
225 // Vector Pairwise Add and Accumulate Long.
226 // Note: This is similar to vpaddl but the destination vector also appears
227 // as the first argument.
228 let TargetPrefix = "arm" in {
229 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
230 [LLVMMatchType<0>, llvm_anyvector_ty],
232 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
233 [LLVMMatchType<0>, llvm_anyvector_ty],
237 // Vector Pairwise Maximum and Minimum.
238 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
239 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
240 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
241 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
245 // The various saturating and rounding vector shift operations need to be
246 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
247 // operation cannot be safely translated to LLVM's shift operators. VSHL can
248 // be used for both left and right shifts, or even combinations of the two,
249 // depending on the signs of the shift amounts. It also has well-defined
250 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
251 // by constants can be represented with LLVM's shift operators.
253 // The shift counts for these intrinsics are always vectors, even for constant
254 // shifts, where the constant is replicated. For consistency with VSHL (and
255 // other variable shift instructions), left shifts have positive shift counts
256 // and right shifts have negative shift counts. This convention is also used
257 // for constant right shift intrinsics, and to help preserve sanity, the
258 // intrinsic names use "shift" instead of either "shl" or "shr". Where
259 // applicable, signed and unsigned versions of the intrinsics are
260 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
261 // such as VQSHLU, take signed operands but produce unsigned results; these
262 // use a "su" suffix.
265 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
266 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
267 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
268 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
269 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
271 // Vector Rounding Shift.
272 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
273 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
274 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
276 // Vector Saturating Shift.
277 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
278 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
279 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
280 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
281 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
282 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
284 // Vector Saturating Rounding Shift.
285 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
286 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
287 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
288 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
289 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
291 // Vector Shift and Insert.
292 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
294 // Vector Absolute Value and Saturating Absolute Value.
295 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
296 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
298 // Vector Saturating Negate.
299 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
301 // Vector Count Leading Sign/Zero Bits.
302 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
303 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
305 // Vector Count One Bits.
306 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
308 // Vector Reciprocal Estimate.
309 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
311 // Vector Reciprocal Square Root Estimate.
312 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
314 // Vector Conversions Between Floating-point and Fixed-point.
315 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
316 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
317 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
318 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
320 // Narrowing and Lengthening Vector Moves.
321 def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic;
322 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
323 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
324 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
325 def int_arm_neon_vmovls : Neon_1Arg_Long_Intrinsic;
326 def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic;
328 // Vector Table Lookup.
329 // The first 1-4 arguments are the table.
330 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
331 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
332 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
333 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
335 // Vector Table Extension.
336 // Some elements of the destination vector may not be updated, so the original
337 // value of that vector is passed as the first argument. The next 1-4
338 // arguments after that are the table.
339 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
340 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
341 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
342 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
344 let TargetPrefix = "arm" in {
346 // De-interleaving vector loads from N-element structures.
347 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
348 [llvm_ptr_ty], [IntrReadArgMem]>;
349 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
350 [llvm_ptr_ty], [IntrReadArgMem]>;
351 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
353 [llvm_ptr_ty], [IntrReadArgMem]>;
354 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
355 LLVMMatchType<0>, LLVMMatchType<0>],
356 [llvm_ptr_ty], [IntrReadArgMem]>;
358 // Vector load N-element structure to one lane.
359 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
360 [llvm_ptr_ty, LLVMMatchType<0>,
361 LLVMMatchType<0>, llvm_i32_ty],
363 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
365 [llvm_ptr_ty, LLVMMatchType<0>,
366 LLVMMatchType<0>, LLVMMatchType<0>,
367 llvm_i32_ty], [IntrReadArgMem]>;
368 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
369 LLVMMatchType<0>, LLVMMatchType<0>],
370 [llvm_ptr_ty, LLVMMatchType<0>,
371 LLVMMatchType<0>, LLVMMatchType<0>,
372 LLVMMatchType<0>, llvm_i32_ty],
375 // Interleaving vector stores from N-element structures.
376 def int_arm_neon_vst1 : Intrinsic<[],
377 [llvm_ptr_ty, llvm_anyvector_ty],
379 def int_arm_neon_vst2 : Intrinsic<[],
380 [llvm_ptr_ty, llvm_anyvector_ty,
381 LLVMMatchType<0>], [IntrWriteArgMem]>;
382 def int_arm_neon_vst3 : Intrinsic<[],
383 [llvm_ptr_ty, llvm_anyvector_ty,
384 LLVMMatchType<0>, LLVMMatchType<0>],
386 def int_arm_neon_vst4 : Intrinsic<[],
387 [llvm_ptr_ty, llvm_anyvector_ty,
388 LLVMMatchType<0>, LLVMMatchType<0>,
389 LLVMMatchType<0>], [IntrWriteArgMem]>;
391 // Vector store N-element structure from one lane.
392 def int_arm_neon_vst2lane : Intrinsic<[],
393 [llvm_ptr_ty, llvm_anyvector_ty,
394 LLVMMatchType<0>, llvm_i32_ty],
396 def int_arm_neon_vst3lane : Intrinsic<[],
397 [llvm_ptr_ty, llvm_anyvector_ty,
398 LLVMMatchType<0>, LLVMMatchType<0>,
399 llvm_i32_ty], [IntrWriteArgMem]>;
400 def int_arm_neon_vst4lane : Intrinsic<[],
401 [llvm_ptr_ty, llvm_anyvector_ty,
402 LLVMMatchType<0>, LLVMMatchType<0>,
403 LLVMMatchType<0>, llvm_i32_ty],