include/llvm/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19   def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  20               Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  21 }
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmentic
  25
  26 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  27   def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  28               Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  29                         [IntrNoMem, Commutative]>;
  30   def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  31               Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  32   def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  33               Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  34   def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  35               Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  36 }
  37
  38 //===----------------------------------------------------------------------===//
  39 // VFP
  40
  41 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  42   def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  43                          Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  44   def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  45                          Intrinsic<[], [llvm_i32_ty], []>;
  46   def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  47                                     [IntrNoMem]>;
  48   def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  49                                     [IntrNoMem]>;
  50 }
  51
  52 //===----------------------------------------------------------------------===//
  53 // Coprocessor
  54
  55 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  56   // Move to coprocessor
  57   def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  58      Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  59                     llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  60   def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  61      Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  62                     llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  63
  64   // Move from coprocessor
  65   def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  66      Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  67                                llvm_i32_ty, llvm_i32_ty], []>;
  68   def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  69      Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  70                                llvm_i32_ty, llvm_i32_ty], []>;
  71
  72   // Coprocessor data processing
  73   def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
  74      Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  75                     llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  76   def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
  77      Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  78                     llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  79
  80   // Move from two registers to coprocessor
  81   def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
  82      Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  83                     llvm_i32_ty, llvm_i32_ty], []>;
  84   def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
  85      Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  86                     llvm_i32_ty, llvm_i32_ty], []>;
  87 }
  88
  89 //===----------------------------------------------------------------------===//
  90 // Advanced SIMD (NEON)
  91
  92 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  93
  94   // The following classes do not correspond directly to GCC builtins.
  95   class Neon_1Arg_Intrinsic
  96     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  97   class Neon_1Arg_Narrow_Intrinsic
  98     : Intrinsic<[llvm_anyvector_ty],
  99                 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
 100   class Neon_2Arg_Intrinsic
 101     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 102                 [IntrNoMem]>;
 103   class Neon_2Arg_Narrow_Intrinsic
 104     : Intrinsic<[llvm_anyvector_ty],
 105                 [LLVMExtendedElementVectorType<0>,
 106                  LLVMExtendedElementVectorType<0>],
 107                 [IntrNoMem]>;
 108   class Neon_2Arg_Long_Intrinsic
 109     : Intrinsic<[llvm_anyvector_ty],
 110                 [LLVMTruncatedElementVectorType<0>,
 111                  LLVMTruncatedElementVectorType<0>],
 112                 [IntrNoMem]>;
 113   class Neon_3Arg_Intrinsic
 114     : Intrinsic<[llvm_anyvector_ty],
 115                 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 116                 [IntrNoMem]>;
 117   class Neon_3Arg_Long_Intrinsic
 118     : Intrinsic<[llvm_anyvector_ty],
 119                 [LLVMMatchType<0>,
 120                  LLVMTruncatedElementVectorType<0>,
 121                  LLVMTruncatedElementVectorType<0>],
 122                 [IntrNoMem]>;
 123   class Neon_CvtFxToFP_Intrinsic
 124     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 125   class Neon_CvtFPToFx_Intrinsic
 126     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 127
 128   // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 129   // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 130   // Overall, the classes range from 2 to 6 v8i8 arguments.
 131   class Neon_Tbl2Arg_Intrinsic
 132     : Intrinsic<[llvm_v8i8_ty],
 133                 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 134   class Neon_Tbl3Arg_Intrinsic
 135     : Intrinsic<[llvm_v8i8_ty],
 136                 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 137   class Neon_Tbl4Arg_Intrinsic
 138     : Intrinsic<[llvm_v8i8_ty],
 139                 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 140                 [IntrNoMem]>;
 141   class Neon_Tbl5Arg_Intrinsic
 142     : Intrinsic<[llvm_v8i8_ty],
 143                 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 144                  llvm_v8i8_ty], [IntrNoMem]>;
 145   class Neon_Tbl6Arg_Intrinsic
 146     : Intrinsic<[llvm_v8i8_ty],
 147                 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 148                  llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 149 }
 150
 151 // Arithmetic ops
 152
 153 let Properties = [IntrNoMem, Commutative] in {
 154
 155   // Vector Add.
 156   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 157   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 158   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 159   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 160   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 161   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 162   def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
 163   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 164
 165   // Vector Multiply.
 166   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 167   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 168   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 169   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 170   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 171   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 172   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 173
 174   // Vector Multiply and Accumulate/Subtract.
 175   def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
 176   def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
 177
 178   // Vector Maximum.
 179   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 180   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 181
 182   // Vector Minimum.
 183   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 184   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 185
 186   // Vector Reciprocal Step.
 187   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 188
 189   // Vector Reciprocal Square Root Step.
 190   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 191 }
 192
 193 // Vector Subtract.
 194 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 195 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 196 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 197 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 198 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
 199 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 200
 201 // Vector Absolute Compare.
 202 let TargetPrefix = "arm" in {
 203   def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
 204                                       [llvm_v2f32_ty, llvm_v2f32_ty],
 205                                       [IntrNoMem]>;
 206   def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
 207                                       [llvm_v4f32_ty, llvm_v4f32_ty],
 208                                       [IntrNoMem]>;
 209   def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
 210                                       [llvm_v2f32_ty, llvm_v2f32_ty],
 211                                       [IntrNoMem]>;
 212   def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
 213                                       [llvm_v4f32_ty, llvm_v4f32_ty],
 214                                       [IntrNoMem]>;
 215 }
 216
 217 // Vector Absolute Differences.
 218 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 219 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 220
 221 // Vector Pairwise Add.
 222 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 223
 224 // Vector Pairwise Add Long.
 225 // Note: This is different than the other "long" NEON intrinsics because
 226 // the result vector has half as many elements as the source vector.
 227 // The source and destination vector types must be specified separately.
 228 let TargetPrefix = "arm" in {
 229   def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 230                                        [IntrNoMem]>;
 231   def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 232                                        [IntrNoMem]>;
 233 }
 234
 235 // Vector Pairwise Add and Accumulate Long.
 236 // Note: This is similar to vpaddl but the destination vector also appears
 237 // as the first argument.
 238 let TargetPrefix = "arm" in {
 239   def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 240                                        [LLVMMatchType<0>, llvm_anyvector_ty],
 241                                        [IntrNoMem]>;
 242   def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 243                                        [LLVMMatchType<0>, llvm_anyvector_ty],
 244                                        [IntrNoMem]>;
 245 }
 246
 247 // Vector Pairwise Maximum and Minimum.
 248 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 249 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 250 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 251 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 252
 253 // Vector Shifts:
 254 //
 255 // The various saturating and rounding vector shift operations need to be
 256 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 257 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 258 // be used for both left and right shifts, or even combinations of the two,
 259 // depending on the signs of the shift amounts.  It also has well-defined
 260 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 261 // by constants can be represented with LLVM's shift operators.
 262 //
 263 // The shift counts for these intrinsics are always vectors, even for constant
 264 // shifts, where the constant is replicated.  For consistency with VSHL (and
 265 // other variable shift instructions), left shifts have positive shift counts
 266 // and right shifts have negative shift counts.  This convention is also used
 267 // for constant right shift intrinsics, and to help preserve sanity, the
 268 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 269 // applicable, signed and unsigned versions of the intrinsics are
 270 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 271 // such as VQSHLU, take signed operands but produce unsigned results; these
 272 // use a "su" suffix.
 273
 274 // Vector Shift.
 275 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 276 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 277 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
 278 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
 279 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
 280
 281 // Vector Rounding Shift.
 282 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 283 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 284 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 285
 286 // Vector Saturating Shift.
 287 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 288 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 289 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 290 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 291 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 292 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 293
 294 // Vector Saturating Rounding Shift.
 295 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 296 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 297 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 298 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 299 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 300
 301 // Vector Shift and Insert.
 302 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 303
 304 // Vector Absolute Value and Saturating Absolute Value.
 305 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 306 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 307
 308 // Vector Saturating Negate.
 309 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 310
 311 // Vector Count Leading Sign/Zero Bits.
 312 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 313 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
 314
 315 // Vector Count One Bits.
 316 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
 317
 318 // Vector Reciprocal Estimate.
 319 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 320
 321 // Vector Reciprocal Square Root Estimate.
 322 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 323
 324 // Vector Conversions Between Floating-point and Fixed-point.
 325 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 326 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 327 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 328 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 329
 330 // Vector Conversions Between Half-Precision and Single-Precision.
 331 def int_arm_neon_vcvtfp2hf
 332     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 333 def int_arm_neon_vcvthf2fp
 334     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 335
 336 // Narrowing Saturating Vector Moves.
 337 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 338 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 339 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 340
 341 // Vector Table Lookup.
 342 // The first 1-4 arguments are the table.
 343 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 344 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 345 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 346 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 347
 348 // Vector Table Extension.
 349 // Some elements of the destination vector may not be updated, so the original
 350 // value of that vector is passed as the first argument.  The next 1-4
 351 // arguments after that are the table.
 352 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 353 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 354 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 355 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 356
 357 let TargetPrefix = "arm" in {
 358
 359   // De-interleaving vector loads from N-element structures.
 360   // Source operands are the address and alignment.
 361   def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 362                                     [llvm_ptr_ty, llvm_i32_ty],
 363                                     [IntrReadArgMem]>;
 364   def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 365                                     [llvm_ptr_ty, llvm_i32_ty],
 366                                     [IntrReadArgMem]>;
 367   def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 368                                      LLVMMatchType<0>],
 369                                     [llvm_ptr_ty, llvm_i32_ty],
 370                                     [IntrReadArgMem]>;
 371   def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 372                                      LLVMMatchType<0>, LLVMMatchType<0>],
 373                                     [llvm_ptr_ty, llvm_i32_ty],
 374                                     [IntrReadArgMem]>;
 375
 376   // Vector load N-element structure to one lane.
 377   // Source operands are: the address, the N input vectors (since only one
 378   // lane is assigned), the lane number, and the alignment.
 379   def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 380                                         [llvm_ptr_ty, LLVMMatchType<0>,
 381                                          LLVMMatchType<0>, llvm_i32_ty,
 382                                          llvm_i32_ty], [IntrReadArgMem]>;
 383   def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 384                                          LLVMMatchType<0>],
 385                                         [llvm_ptr_ty, LLVMMatchType<0>,
 386                                          LLVMMatchType<0>, LLVMMatchType<0>,
 387                                          llvm_i32_ty, llvm_i32_ty],
 388                                         [IntrReadArgMem]>;
 389   def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 390                                          LLVMMatchType<0>, LLVMMatchType<0>],
 391                                         [llvm_ptr_ty, LLVMMatchType<0>,
 392                                          LLVMMatchType<0>, LLVMMatchType<0>,
 393                                          LLVMMatchType<0>, llvm_i32_ty,
 394                                          llvm_i32_ty], [IntrReadArgMem]>;
 395
 396   // Interleaving vector stores from N-element structures.
 397   // Source operands are: the address, the N vectors, and the alignment.
 398   def int_arm_neon_vst1 : Intrinsic<[],
 399                                     [llvm_ptr_ty, llvm_anyvector_ty,
 400                                      llvm_i32_ty], [IntrReadWriteArgMem]>;
 401   def int_arm_neon_vst2 : Intrinsic<[],
 402                                     [llvm_ptr_ty, llvm_anyvector_ty,
 403                                      LLVMMatchType<0>, llvm_i32_ty],
 404                                     [IntrReadWriteArgMem]>;
 405   def int_arm_neon_vst3 : Intrinsic<[],
 406                                     [llvm_ptr_ty, llvm_anyvector_ty,
 407                                      LLVMMatchType<0>, LLVMMatchType<0>,
 408                                      llvm_i32_ty], [IntrReadWriteArgMem]>;
 409   def int_arm_neon_vst4 : Intrinsic<[],
 410                                     [llvm_ptr_ty, llvm_anyvector_ty,
 411                                      LLVMMatchType<0>, LLVMMatchType<0>,
 412                                      LLVMMatchType<0>, llvm_i32_ty],
 413                                     [IntrReadWriteArgMem]>;
 414
 415   // Vector store N-element structure from one lane.
 416   // Source operands are: the address, the N vectors, the lane number, and
 417   // the alignment.
 418   def int_arm_neon_vst2lane : Intrinsic<[],
 419                                         [llvm_ptr_ty, llvm_anyvector_ty,
 420                                          LLVMMatchType<0>, llvm_i32_ty,
 421                                          llvm_i32_ty], [IntrReadWriteArgMem]>;
 422   def int_arm_neon_vst3lane : Intrinsic<[],
 423                                         [llvm_ptr_ty, llvm_anyvector_ty,
 424                                          LLVMMatchType<0>, LLVMMatchType<0>,
 425                                          llvm_i32_ty, llvm_i32_ty],
 426                                         [IntrReadWriteArgMem]>;
 427   def int_arm_neon_vst4lane : Intrinsic<[],
 428                                         [llvm_ptr_ty, llvm_anyvector_ty,
 429                                          LLVMMatchType<0>, LLVMMatchType<0>,
 430                                          LLVMMatchType<0>, llvm_i32_ty,
 431                                          llvm_i32_ty], [IntrReadWriteArgMem]>;
 432 }