1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Advanced SIMD (NEON)
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
28 // The following classes do not correspond directly to GCC builtins.
29 class Neon_1Arg_Intrinsic
30 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
31 class Neon_1Arg_Narrow_Intrinsic
32 : Intrinsic<[llvm_anyvector_ty],
33 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
34 class Neon_1Arg_Long_Intrinsic
35 : Intrinsic<[llvm_anyvector_ty],
36 [LLVMTruncatedElementVectorType<0>], [IntrNoMem]>;
37 class Neon_2Arg_Intrinsic
38 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
40 class Neon_2Arg_Narrow_Intrinsic
41 : Intrinsic<[llvm_anyvector_ty],
42 [LLVMExtendedElementVectorType<0>,
43 LLVMExtendedElementVectorType<0>],
45 class Neon_2Arg_Long_Intrinsic
46 : Intrinsic<[llvm_anyvector_ty],
47 [LLVMTruncatedElementVectorType<0>,
48 LLVMTruncatedElementVectorType<0>],
50 class Neon_2Arg_Wide_Intrinsic
51 : Intrinsic<[llvm_anyvector_ty],
52 [LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
54 class Neon_3Arg_Intrinsic
55 : Intrinsic<[llvm_anyvector_ty],
56 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
58 class Neon_3Arg_Long_Intrinsic
59 : Intrinsic<[llvm_anyvector_ty],
61 LLVMTruncatedElementVectorType<0>,
62 LLVMTruncatedElementVectorType<0>],
64 class Neon_CvtFxToFP_Intrinsic
65 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
66 class Neon_CvtFPToFx_Intrinsic
67 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
69 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
70 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
71 // Overall, the classes range from 2 to 6 v8i8 arguments.
72 class Neon_Tbl2Arg_Intrinsic
73 : Intrinsic<[llvm_v8i8_ty],
74 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
75 class Neon_Tbl3Arg_Intrinsic
76 : Intrinsic<[llvm_v8i8_ty],
77 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
78 class Neon_Tbl4Arg_Intrinsic
79 : Intrinsic<[llvm_v8i8_ty],
80 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
82 class Neon_Tbl5Arg_Intrinsic
83 : Intrinsic<[llvm_v8i8_ty],
84 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
85 llvm_v8i8_ty], [IntrNoMem]>;
86 class Neon_Tbl6Arg_Intrinsic
87 : Intrinsic<[llvm_v8i8_ty],
88 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
89 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
94 let Properties = [IntrNoMem, Commutative] in {
97 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
98 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
99 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
100 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
101 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
102 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
103 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
104 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
105 def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic;
106 def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic;
107 def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic;
108 def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic;
111 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
112 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
113 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
114 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
115 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
116 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
117 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
119 // Vector Multiply and Accumulate/Subtract.
120 def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic;
121 def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic;
122 def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic;
123 def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic;
124 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
125 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
128 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
129 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
132 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
133 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
135 // Vector Reciprocal Step.
136 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
138 // Vector Reciprocal Square Root Step.
139 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
143 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
144 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
145 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
146 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
147 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
148 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
149 def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic;
150 def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic;
151 def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic;
152 def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic;
154 // Vector Absolute Compare.
155 let TargetPrefix = "arm" in {
156 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
157 [llvm_v2f32_ty, llvm_v2f32_ty],
159 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
160 [llvm_v4f32_ty, llvm_v4f32_ty],
162 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
163 [llvm_v2f32_ty, llvm_v2f32_ty],
165 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
166 [llvm_v4f32_ty, llvm_v4f32_ty],
170 // Vector Absolute Differences.
171 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
172 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
173 def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic;
174 def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic;
176 // Vector Absolute Difference and Accumulate.
177 def int_arm_neon_vabas : Neon_3Arg_Intrinsic;
178 def int_arm_neon_vabau : Neon_3Arg_Intrinsic;
179 def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic;
180 def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic;
182 // Vector Pairwise Add.
183 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
185 // Vector Pairwise Add Long.
186 // Note: This is different than the other "long" NEON intrinsics because
187 // the result vector has half as many elements as the source vector.
188 // The source and destination vector types must be specified separately.
189 let TargetPrefix = "arm" in {
190 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
192 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
196 // Vector Pairwise Add and Accumulate Long.
197 // Note: This is similar to vpaddl but the destination vector also appears
198 // as the first argument.
199 let TargetPrefix = "arm" in {
200 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
201 [LLVMMatchType<0>, llvm_anyvector_ty],
203 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
204 [LLVMMatchType<0>, llvm_anyvector_ty],
208 // Vector Pairwise Maximum and Minimum.
209 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
210 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
211 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
212 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
216 // The various saturating and rounding vector shift operations need to be
217 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
218 // operation cannot be safely translated to LLVM's shift operators. VSHL can
219 // be used for both left and right shifts, or even combinations of the two,
220 // depending on the signs of the shift amounts. It also has well-defined
221 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
222 // by constants can be represented with LLVM's shift operators.
224 // The shift counts for these intrinsics are always vectors, even for constant
225 // shifts, where the constant is replicated. For consistency with VSHL (and
226 // other variable shift instructions), left shifts have positive shift counts
227 // and right shifts have negative shift counts. This convention is also used
228 // for constant right shift intrinsics, and to help preserve sanity, the
229 // intrinsic names use "shift" instead of either "shl" or "shr". Where
230 // applicable, signed and unsigned versions of the intrinsics are
231 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
232 // such as VQSHLU, take signed operands but produce unsigned results; these
233 // use a "su" suffix.
236 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
237 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
238 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
239 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
240 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
242 // Vector Rounding Shift.
243 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
244 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
245 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
247 // Vector Saturating Shift.
248 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
249 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
250 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
251 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
252 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
253 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
255 // Vector Saturating Rounding Shift.
256 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
257 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
258 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
259 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
260 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
262 // Vector Shift and Insert.
263 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
265 // Vector Absolute Value and Saturating Absolute Value.
266 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
267 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
269 // Vector Saturating Negate.
270 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
272 // Vector Count Leading Sign/Zero Bits.
273 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
274 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
276 // Vector Count One Bits.
277 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
279 // Vector Reciprocal Estimate.
280 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
282 // Vector Reciprocal Square Root Estimate.
283 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
285 // Vector Conversions Between Floating-point and Fixed-point.
286 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
287 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
288 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
289 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
291 // Narrowing and Lengthening Vector Moves.
292 def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic;
293 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
294 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
295 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
296 def int_arm_neon_vmovls : Neon_1Arg_Long_Intrinsic;
297 def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic;
299 // Vector Table Lookup.
300 // The first 1-4 arguments are the table.
301 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
302 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
303 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
304 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
306 // Vector Table Extension.
307 // Some elements of the destination vector may not be updated, so the original
308 // value of that vector is passed as the first argument. The next 1-4
309 // arguments after that are the table.
310 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
311 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
312 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
313 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
315 let TargetPrefix = "arm" in {
317 // De-interleaving vector loads from N-element structures.
318 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
319 [llvm_ptr_ty], [IntrReadArgMem]>;
320 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
321 [llvm_ptr_ty], [IntrReadArgMem]>;
322 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
324 [llvm_ptr_ty], [IntrReadArgMem]>;
325 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
326 LLVMMatchType<0>, LLVMMatchType<0>],
327 [llvm_ptr_ty], [IntrReadArgMem]>;
329 // Vector load N-element structure to one lane.
330 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
331 [llvm_ptr_ty, LLVMMatchType<0>,
332 LLVMMatchType<0>, llvm_i32_ty],
334 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
336 [llvm_ptr_ty, LLVMMatchType<0>,
337 LLVMMatchType<0>, LLVMMatchType<0>,
338 llvm_i32_ty], [IntrReadArgMem]>;
339 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
340 LLVMMatchType<0>, LLVMMatchType<0>],
341 [llvm_ptr_ty, LLVMMatchType<0>,
342 LLVMMatchType<0>, LLVMMatchType<0>,
343 LLVMMatchType<0>, llvm_i32_ty],
346 // Interleaving vector stores from N-element structures.
347 def int_arm_neon_vst1 : Intrinsic<[],
348 [llvm_ptr_ty, llvm_anyvector_ty],
350 def int_arm_neon_vst2 : Intrinsic<[],
351 [llvm_ptr_ty, llvm_anyvector_ty,
352 LLVMMatchType<0>], [IntrWriteArgMem]>;
353 def int_arm_neon_vst3 : Intrinsic<[],
354 [llvm_ptr_ty, llvm_anyvector_ty,
355 LLVMMatchType<0>, LLVMMatchType<0>],
357 def int_arm_neon_vst4 : Intrinsic<[],
358 [llvm_ptr_ty, llvm_anyvector_ty,
359 LLVMMatchType<0>, LLVMMatchType<0>,
360 LLVMMatchType<0>], [IntrWriteArgMem]>;
362 // Vector store N-element structure from one lane.
363 def int_arm_neon_vst2lane : Intrinsic<[],
364 [llvm_ptr_ty, llvm_anyvector_ty,
365 LLVMMatchType<0>, llvm_i32_ty],
367 def int_arm_neon_vst3lane : Intrinsic<[],
368 [llvm_ptr_ty, llvm_anyvector_ty,
369 LLVMMatchType<0>, LLVMMatchType<0>,
370 llvm_i32_ty], [IntrWriteArgMem]>;
371 def int_arm_neon_vst4lane : Intrinsic<[],
372 [llvm_ptr_ty, llvm_anyvector_ty,
373 LLVMMatchType<0>, LLVMMatchType<0>,
374 LLVMMatchType<0>, llvm_i32_ty],