1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
27 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
28 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
29 [IntrNoMem, Commutative]>;
30 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
31 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
32 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
33 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
34 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
35 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
38 //===----------------------------------------------------------------------===//
41 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
42 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
43 Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
44 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
45 Intrinsic<[], [llvm_i32_ty], []>;
46 def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
48 def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
52 //===----------------------------------------------------------------------===//
53 // Advanced SIMD (NEON)
55 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
57 // The following classes do not correspond directly to GCC builtins.
58 class Neon_1Arg_Intrinsic
59 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
60 class Neon_1Arg_Narrow_Intrinsic
61 : Intrinsic<[llvm_anyvector_ty],
62 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
63 class Neon_2Arg_Intrinsic
64 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
66 class Neon_2Arg_Narrow_Intrinsic
67 : Intrinsic<[llvm_anyvector_ty],
68 [LLVMExtendedElementVectorType<0>,
69 LLVMExtendedElementVectorType<0>],
71 class Neon_2Arg_Long_Intrinsic
72 : Intrinsic<[llvm_anyvector_ty],
73 [LLVMTruncatedElementVectorType<0>,
74 LLVMTruncatedElementVectorType<0>],
76 class Neon_3Arg_Intrinsic
77 : Intrinsic<[llvm_anyvector_ty],
78 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
80 class Neon_3Arg_Long_Intrinsic
81 : Intrinsic<[llvm_anyvector_ty],
83 LLVMTruncatedElementVectorType<0>,
84 LLVMTruncatedElementVectorType<0>],
86 class Neon_CvtFxToFP_Intrinsic
87 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
88 class Neon_CvtFPToFx_Intrinsic
89 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
91 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
92 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
93 // Overall, the classes range from 2 to 6 v8i8 arguments.
94 class Neon_Tbl2Arg_Intrinsic
95 : Intrinsic<[llvm_v8i8_ty],
96 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
97 class Neon_Tbl3Arg_Intrinsic
98 : Intrinsic<[llvm_v8i8_ty],
99 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
100 class Neon_Tbl4Arg_Intrinsic
101 : Intrinsic<[llvm_v8i8_ty],
102 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
104 class Neon_Tbl5Arg_Intrinsic
105 : Intrinsic<[llvm_v8i8_ty],
106 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
107 llvm_v8i8_ty], [IntrNoMem]>;
108 class Neon_Tbl6Arg_Intrinsic
109 : Intrinsic<[llvm_v8i8_ty],
110 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
111 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
116 let Properties = [IntrNoMem, Commutative] in {
119 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
120 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
121 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
122 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
123 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
124 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
125 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
126 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
129 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
130 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
131 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
132 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
133 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
134 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
135 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
138 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
139 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
142 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
143 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
145 // Vector Reciprocal Step.
146 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
148 // Vector Reciprocal Square Root Step.
149 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
153 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
154 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
155 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
156 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
157 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
158 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
160 // Vector Absolute Compare.
161 let TargetPrefix = "arm" in {
162 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
163 [llvm_v2f32_ty, llvm_v2f32_ty],
165 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
166 [llvm_v4f32_ty, llvm_v4f32_ty],
168 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
169 [llvm_v2f32_ty, llvm_v2f32_ty],
171 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
172 [llvm_v4f32_ty, llvm_v4f32_ty],
176 // Vector Absolute Differences.
177 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
178 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
180 // Vector Pairwise Add.
181 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
183 // Vector Pairwise Add Long.
184 // Note: This is different than the other "long" NEON intrinsics because
185 // the result vector has half as many elements as the source vector.
186 // The source and destination vector types must be specified separately.
187 let TargetPrefix = "arm" in {
188 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
190 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
194 // Vector Pairwise Add and Accumulate Long.
195 // Note: This is similar to vpaddl but the destination vector also appears
196 // as the first argument.
197 let TargetPrefix = "arm" in {
198 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
199 [LLVMMatchType<0>, llvm_anyvector_ty],
201 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
202 [LLVMMatchType<0>, llvm_anyvector_ty],
206 // Vector Pairwise Maximum and Minimum.
207 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
208 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
209 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
210 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
214 // The various saturating and rounding vector shift operations need to be
215 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
216 // operation cannot be safely translated to LLVM's shift operators. VSHL can
217 // be used for both left and right shifts, or even combinations of the two,
218 // depending on the signs of the shift amounts. It also has well-defined
219 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
220 // by constants can be represented with LLVM's shift operators.
222 // The shift counts for these intrinsics are always vectors, even for constant
223 // shifts, where the constant is replicated. For consistency with VSHL (and
224 // other variable shift instructions), left shifts have positive shift counts
225 // and right shifts have negative shift counts. This convention is also used
226 // for constant right shift intrinsics, and to help preserve sanity, the
227 // intrinsic names use "shift" instead of either "shl" or "shr". Where
228 // applicable, signed and unsigned versions of the intrinsics are
229 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
230 // such as VQSHLU, take signed operands but produce unsigned results; these
231 // use a "su" suffix.
234 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
235 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
236 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
237 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
238 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
240 // Vector Rounding Shift.
241 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
242 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
243 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
245 // Vector Saturating Shift.
246 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
247 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
248 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
249 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
250 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
251 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
253 // Vector Saturating Rounding Shift.
254 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
255 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
256 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
257 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
258 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
260 // Vector Shift and Insert.
261 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
263 // Vector Absolute Value and Saturating Absolute Value.
264 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
265 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
267 // Vector Saturating Negate.
268 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
270 // Vector Count Leading Sign/Zero Bits.
271 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
272 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
274 // Vector Count One Bits.
275 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
277 // Vector Reciprocal Estimate.
278 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
280 // Vector Reciprocal Square Root Estimate.
281 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
283 // Vector Conversions Between Floating-point and Fixed-point.
284 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
285 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
286 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
287 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
289 // Vector Conversions Between Half-Precision and Single-Precision.
290 def int_arm_neon_vcvtfp2hf
291 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
292 def int_arm_neon_vcvthf2fp
293 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
295 // Narrowing Saturating Vector Moves.
296 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
297 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
298 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
300 // Vector Table Lookup.
301 // The first 1-4 arguments are the table.
302 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
303 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
304 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
305 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
307 // Vector Table Extension.
308 // Some elements of the destination vector may not be updated, so the original
309 // value of that vector is passed as the first argument. The next 1-4
310 // arguments after that are the table.
311 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
312 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
313 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
314 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
316 let TargetPrefix = "arm" in {
318 // De-interleaving vector loads from N-element structures.
319 // Source operands are the address and alignment.
320 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
321 [llvm_ptr_ty, llvm_i32_ty],
323 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
324 [llvm_ptr_ty, llvm_i32_ty],
326 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
328 [llvm_ptr_ty, llvm_i32_ty],
330 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
331 LLVMMatchType<0>, LLVMMatchType<0>],
332 [llvm_ptr_ty, llvm_i32_ty],
335 // Vector load N-element structure to one lane.
336 // Source operands are: the address, the N input vectors (since only one
337 // lane is assigned), the lane number, and the alignment.
338 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
339 [llvm_ptr_ty, LLVMMatchType<0>,
340 LLVMMatchType<0>, llvm_i32_ty,
341 llvm_i32_ty], [IntrReadArgMem]>;
342 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
344 [llvm_ptr_ty, LLVMMatchType<0>,
345 LLVMMatchType<0>, LLVMMatchType<0>,
346 llvm_i32_ty, llvm_i32_ty],
348 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
349 LLVMMatchType<0>, LLVMMatchType<0>],
350 [llvm_ptr_ty, LLVMMatchType<0>,
351 LLVMMatchType<0>, LLVMMatchType<0>,
352 LLVMMatchType<0>, llvm_i32_ty,
353 llvm_i32_ty], [IntrReadArgMem]>;
355 // Interleaving vector stores from N-element structures.
356 // Source operands are: the address, the N vectors, and the alignment.
357 def int_arm_neon_vst1 : Intrinsic<[],
358 [llvm_ptr_ty, llvm_anyvector_ty,
359 llvm_i32_ty], [IntrReadWriteArgMem]>;
360 def int_arm_neon_vst2 : Intrinsic<[],
361 [llvm_ptr_ty, llvm_anyvector_ty,
362 LLVMMatchType<0>, llvm_i32_ty],
363 [IntrReadWriteArgMem]>;
364 def int_arm_neon_vst3 : Intrinsic<[],
365 [llvm_ptr_ty, llvm_anyvector_ty,
366 LLVMMatchType<0>, LLVMMatchType<0>,
367 llvm_i32_ty], [IntrReadWriteArgMem]>;
368 def int_arm_neon_vst4 : Intrinsic<[],
369 [llvm_ptr_ty, llvm_anyvector_ty,
370 LLVMMatchType<0>, LLVMMatchType<0>,
371 LLVMMatchType<0>, llvm_i32_ty],
372 [IntrReadWriteArgMem]>;
374 // Vector store N-element structure from one lane.
375 // Source operands are: the address, the N vectors, the lane number, and
377 def int_arm_neon_vst2lane : Intrinsic<[],
378 [llvm_ptr_ty, llvm_anyvector_ty,
379 LLVMMatchType<0>, llvm_i32_ty,
380 llvm_i32_ty], [IntrReadWriteArgMem]>;
381 def int_arm_neon_vst3lane : Intrinsic<[],
382 [llvm_ptr_ty, llvm_anyvector_ty,
383 LLVMMatchType<0>, LLVMMatchType<0>,
384 llvm_i32_ty, llvm_i32_ty],
385 [IntrReadWriteArgMem]>;
386 def int_arm_neon_vst4lane : Intrinsic<[],
387 [llvm_ptr_ty, llvm_anyvector_ty,
388 LLVMMatchType<0>, LLVMMatchType<0>,
389 LLVMMatchType<0>, llvm_i32_ty,
390 llvm_i32_ty], [IntrReadWriteArgMem]>;