1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
27 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
28 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
29 [IntrNoMem, Commutative]>;
30 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
31 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
34 //===----------------------------------------------------------------------===//
35 // Advanced SIMD (NEON)
37 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
39 // The following classes do not correspond directly to GCC builtins.
40 class Neon_1Arg_Intrinsic
41 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
42 class Neon_1Arg_Narrow_Intrinsic
43 : Intrinsic<[llvm_anyvector_ty],
44 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
45 class Neon_1Arg_Long_Intrinsic
46 : Intrinsic<[llvm_anyvector_ty],
47 [LLVMTruncatedElementVectorType<0>], [IntrNoMem]>;
48 class Neon_2Arg_Intrinsic
49 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
51 class Neon_2Arg_Narrow_Intrinsic
52 : Intrinsic<[llvm_anyvector_ty],
53 [LLVMExtendedElementVectorType<0>,
54 LLVMExtendedElementVectorType<0>],
56 class Neon_2Arg_Long_Intrinsic
57 : Intrinsic<[llvm_anyvector_ty],
58 [LLVMTruncatedElementVectorType<0>,
59 LLVMTruncatedElementVectorType<0>],
61 class Neon_2Arg_Wide_Intrinsic
62 : Intrinsic<[llvm_anyvector_ty],
63 [LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
65 class Neon_3Arg_Intrinsic
66 : Intrinsic<[llvm_anyvector_ty],
67 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
69 class Neon_3Arg_Long_Intrinsic
70 : Intrinsic<[llvm_anyvector_ty],
72 LLVMTruncatedElementVectorType<0>,
73 LLVMTruncatedElementVectorType<0>],
75 class Neon_CvtFxToFP_Intrinsic
76 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
77 class Neon_CvtFPToFx_Intrinsic
78 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
80 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
81 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
82 // Overall, the classes range from 2 to 6 v8i8 arguments.
83 class Neon_Tbl2Arg_Intrinsic
84 : Intrinsic<[llvm_v8i8_ty],
85 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
86 class Neon_Tbl3Arg_Intrinsic
87 : Intrinsic<[llvm_v8i8_ty],
88 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
89 class Neon_Tbl4Arg_Intrinsic
90 : Intrinsic<[llvm_v8i8_ty],
91 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
93 class Neon_Tbl5Arg_Intrinsic
94 : Intrinsic<[llvm_v8i8_ty],
95 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
96 llvm_v8i8_ty], [IntrNoMem]>;
97 class Neon_Tbl6Arg_Intrinsic
98 : Intrinsic<[llvm_v8i8_ty],
99 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
100 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
105 let Properties = [IntrNoMem, Commutative] in {
108 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
109 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
110 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
111 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
112 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
113 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
114 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
115 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
116 def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic;
117 def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic;
118 def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic;
119 def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic;
122 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
123 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
124 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
125 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
126 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
127 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
128 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
130 // Vector Multiply and Accumulate/Subtract.
131 def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic;
132 def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic;
133 def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic;
134 def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic;
135 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
136 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
139 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
140 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
143 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
144 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
146 // Vector Reciprocal Step.
147 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
149 // Vector Reciprocal Square Root Step.
150 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
154 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
155 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
156 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
157 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
158 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
159 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
160 def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic;
161 def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic;
162 def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic;
163 def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic;
165 // Vector Absolute Compare.
166 let TargetPrefix = "arm" in {
167 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
168 [llvm_v2f32_ty, llvm_v2f32_ty],
170 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
171 [llvm_v4f32_ty, llvm_v4f32_ty],
173 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
174 [llvm_v2f32_ty, llvm_v2f32_ty],
176 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
177 [llvm_v4f32_ty, llvm_v4f32_ty],
181 // Vector Absolute Differences.
182 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
183 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
184 def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic;
185 def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic;
187 // Vector Absolute Difference and Accumulate.
188 def int_arm_neon_vabas : Neon_3Arg_Intrinsic;
189 def int_arm_neon_vabau : Neon_3Arg_Intrinsic;
190 def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic;
191 def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic;
193 // Vector Pairwise Add.
194 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
196 // Vector Pairwise Add Long.
197 // Note: This is different than the other "long" NEON intrinsics because
198 // the result vector has half as many elements as the source vector.
199 // The source and destination vector types must be specified separately.
200 let TargetPrefix = "arm" in {
201 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
203 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
207 // Vector Pairwise Add and Accumulate Long.
208 // Note: This is similar to vpaddl but the destination vector also appears
209 // as the first argument.
210 let TargetPrefix = "arm" in {
211 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
212 [LLVMMatchType<0>, llvm_anyvector_ty],
214 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
215 [LLVMMatchType<0>, llvm_anyvector_ty],
219 // Vector Pairwise Maximum and Minimum.
220 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
221 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
222 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
223 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
227 // The various saturating and rounding vector shift operations need to be
228 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
229 // operation cannot be safely translated to LLVM's shift operators. VSHL can
230 // be used for both left and right shifts, or even combinations of the two,
231 // depending on the signs of the shift amounts. It also has well-defined
232 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
233 // by constants can be represented with LLVM's shift operators.
235 // The shift counts for these intrinsics are always vectors, even for constant
236 // shifts, where the constant is replicated. For consistency with VSHL (and
237 // other variable shift instructions), left shifts have positive shift counts
238 // and right shifts have negative shift counts. This convention is also used
239 // for constant right shift intrinsics, and to help preserve sanity, the
240 // intrinsic names use "shift" instead of either "shl" or "shr". Where
241 // applicable, signed and unsigned versions of the intrinsics are
242 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
243 // such as VQSHLU, take signed operands but produce unsigned results; these
244 // use a "su" suffix.
247 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
248 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
249 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
250 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
251 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
253 // Vector Rounding Shift.
254 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
255 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
256 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
258 // Vector Saturating Shift.
259 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
260 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
261 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
262 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
263 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
264 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
266 // Vector Saturating Rounding Shift.
267 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
268 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
269 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
270 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
271 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
273 // Vector Shift and Insert.
274 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
276 // Vector Absolute Value and Saturating Absolute Value.
277 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
278 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
280 // Vector Saturating Negate.
281 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
283 // Vector Count Leading Sign/Zero Bits.
284 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
285 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
287 // Vector Count One Bits.
288 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
290 // Vector Reciprocal Estimate.
291 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
293 // Vector Reciprocal Square Root Estimate.
294 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
296 // Vector Conversions Between Floating-point and Fixed-point.
297 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
298 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
299 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
300 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
302 // Narrowing and Lengthening Vector Moves.
303 def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic;
304 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
305 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
306 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
307 def int_arm_neon_vmovls : Neon_1Arg_Long_Intrinsic;
308 def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic;
310 // Vector Table Lookup.
311 // The first 1-4 arguments are the table.
312 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
313 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
314 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
315 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
317 // Vector Table Extension.
318 // Some elements of the destination vector may not be updated, so the original
319 // value of that vector is passed as the first argument. The next 1-4
320 // arguments after that are the table.
321 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
322 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
323 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
324 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
326 let TargetPrefix = "arm" in {
328 // De-interleaving vector loads from N-element structures.
329 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
330 [llvm_ptr_ty], [IntrReadArgMem]>;
331 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
332 [llvm_ptr_ty], [IntrReadArgMem]>;
333 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
335 [llvm_ptr_ty], [IntrReadArgMem]>;
336 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
337 LLVMMatchType<0>, LLVMMatchType<0>],
338 [llvm_ptr_ty], [IntrReadArgMem]>;
340 // Vector load N-element structure to one lane.
341 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
342 [llvm_ptr_ty, LLVMMatchType<0>,
343 LLVMMatchType<0>, llvm_i32_ty],
345 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
347 [llvm_ptr_ty, LLVMMatchType<0>,
348 LLVMMatchType<0>, LLVMMatchType<0>,
349 llvm_i32_ty], [IntrReadArgMem]>;
350 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
351 LLVMMatchType<0>, LLVMMatchType<0>],
352 [llvm_ptr_ty, LLVMMatchType<0>,
353 LLVMMatchType<0>, LLVMMatchType<0>,
354 LLVMMatchType<0>, llvm_i32_ty],
357 // Interleaving vector stores from N-element structures.
358 def int_arm_neon_vst1 : Intrinsic<[],
359 [llvm_ptr_ty, llvm_anyvector_ty],
361 def int_arm_neon_vst2 : Intrinsic<[],
362 [llvm_ptr_ty, llvm_anyvector_ty,
363 LLVMMatchType<0>], [IntrWriteArgMem]>;
364 def int_arm_neon_vst3 : Intrinsic<[],
365 [llvm_ptr_ty, llvm_anyvector_ty,
366 LLVMMatchType<0>, LLVMMatchType<0>],
368 def int_arm_neon_vst4 : Intrinsic<[],
369 [llvm_ptr_ty, llvm_anyvector_ty,
370 LLVMMatchType<0>, LLVMMatchType<0>,
371 LLVMMatchType<0>], [IntrWriteArgMem]>;
373 // Vector store N-element structure from one lane.
374 def int_arm_neon_vst2lane : Intrinsic<[],
375 [llvm_ptr_ty, llvm_anyvector_ty,
376 LLVMMatchType<0>, llvm_i32_ty],
378 def int_arm_neon_vst3lane : Intrinsic<[],
379 [llvm_ptr_ty, llvm_anyvector_ty,
380 LLVMMatchType<0>, LLVMMatchType<0>,
381 llvm_i32_ty], [IntrWriteArgMem]>;
382 def int_arm_neon_vst4lane : Intrinsic<[],
383 [llvm_ptr_ty, llvm_anyvector_ty,
384 LLVMMatchType<0>, LLVMMatchType<0>,
385 LLVMMatchType<0>, llvm_i32_ty],