1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Advanced SIMD (NEON)
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
28 // The following classes do not correspond directly to GCC builtins.
29 class Neon_1Arg_Intrinsic
30 : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
31 class Neon_1Arg_Float_Intrinsic
32 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
33 class Neon_1Arg_Narrow_Intrinsic
34 : Intrinsic<[llvm_anyint_ty],
35 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
36 class Neon_1Arg_Long_Intrinsic
37 : Intrinsic<[llvm_anyint_ty],
38 [LLVMTruncatedElementVectorType<0>], [IntrNoMem]>;
39 class Neon_2Arg_Intrinsic
40 : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
42 class Neon_2Arg_Float_Intrinsic
43 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
45 class Neon_2Arg_Narrow_Intrinsic
46 : Intrinsic<[llvm_anyint_ty],
47 [LLVMExtendedElementVectorType<0>,
48 LLVMExtendedElementVectorType<0>],
50 class Neon_2Arg_Long_Intrinsic
51 : Intrinsic<[llvm_anyint_ty],
52 [LLVMTruncatedElementVectorType<0>,
53 LLVMTruncatedElementVectorType<0>],
55 class Neon_2Arg_Wide_Intrinsic
56 : Intrinsic<[llvm_anyint_ty],
57 [LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
59 class Neon_3Arg_Intrinsic
60 : Intrinsic<[llvm_anyint_ty],
61 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
63 class Neon_3Arg_Long_Intrinsic
64 : Intrinsic<[llvm_anyint_ty],
66 LLVMTruncatedElementVectorType<0>,
67 LLVMTruncatedElementVectorType<0>],
69 class Neon_CvtFxToFP_Intrinsic
70 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
71 class Neon_CvtFPToFx_Intrinsic
72 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
77 let Properties = [IntrNoMem, Commutative] in {
80 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
81 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
82 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
83 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
84 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
85 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
86 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
87 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
88 def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic;
89 def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic;
90 def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic;
91 def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic;
94 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
95 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
96 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
97 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
98 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
99 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
100 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
102 // Vector Multiply and Accumulate/Subtract.
103 def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic;
104 def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic;
105 def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic;
106 def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic;
107 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
108 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
111 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
112 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
113 def int_arm_neon_vmaxf : Neon_2Arg_Float_Intrinsic;
116 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
117 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
118 def int_arm_neon_vminf : Neon_2Arg_Float_Intrinsic;
120 // Vector Reciprocal Step.
121 def int_arm_neon_vrecps : Neon_2Arg_Float_Intrinsic;
123 // Vector Reciprocal Square Root Step.
124 def int_arm_neon_vrsqrts : Neon_2Arg_Float_Intrinsic;
128 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
129 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
130 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
131 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
132 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
133 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
134 def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic;
135 def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic;
136 def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic;
137 def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic;
139 // Vector Absolute Compare.
140 let TargetPrefix = "arm" in {
141 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
142 [llvm_v2f32_ty, llvm_v2f32_ty],
144 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
145 [llvm_v4f32_ty, llvm_v4f32_ty],
147 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
148 [llvm_v2f32_ty, llvm_v2f32_ty],
150 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
151 [llvm_v4f32_ty, llvm_v4f32_ty],
155 // Vector Absolute Differences.
156 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
157 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
158 def int_arm_neon_vabdf : Neon_2Arg_Float_Intrinsic;
159 def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic;
160 def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic;
162 // Vector Absolute Difference and Accumulate.
163 def int_arm_neon_vabas : Neon_3Arg_Intrinsic;
164 def int_arm_neon_vabau : Neon_3Arg_Intrinsic;
165 def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic;
166 def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic;
168 // Vector Pairwise Add.
169 def int_arm_neon_vpaddi : Neon_2Arg_Intrinsic;
170 def int_arm_neon_vpaddf : Neon_2Arg_Float_Intrinsic;
172 // Vector Pairwise Add Long.
173 // Note: This is different than the other "long" NEON intrinsics because
174 // the result vector has half as many elements as the source vector.
175 // The source and destination vector types must be specified separately.
176 let TargetPrefix = "arm" in {
177 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty],
179 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty],
183 // Vector Pairwise Add and Accumulate Long.
184 // Note: This is similar to vpaddl but the destination vector also appears
185 // as the first argument.
186 let TargetPrefix = "arm" in {
187 def int_arm_neon_vpadals : Intrinsic<[llvm_anyint_ty],
188 [LLVMMatchType<0>, llvm_anyint_ty],
190 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyint_ty],
191 [LLVMMatchType<0>, llvm_anyint_ty],
195 // Vector Pairwise Maximum and Minimum.
196 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
197 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
198 def int_arm_neon_vpmaxf : Neon_2Arg_Float_Intrinsic;
199 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
200 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
201 def int_arm_neon_vpminf : Neon_2Arg_Float_Intrinsic;
205 // The various saturating and rounding vector shift operations need to be
206 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
207 // operation cannot be safely translated to LLVM's shift operators. VSHL can
208 // be used for both left and right shifts, or even combinations of the two,
209 // depending on the signs of the shift amounts. It also has well-defined
210 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
211 // by constants can be represented with LLVM's shift operators.
213 // The shift counts for these intrinsics are always vectors, even for constant
214 // shifts, where the constant is replicated. For consistency with VSHL (and
215 // other variable shift instructions), left shifts have positive shift counts
216 // and right shifts have negative shift counts. This convention is also used
217 // for constant right shift intrinsics, and to help preserve sanity, the
218 // intrinsic names use "shift" instead of either "shl" or "shr". Where
219 // applicable, signed and unsigned versions of the intrinsics are
220 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
221 // such as VQSHLU, take signed operands but produce unsigned results; these
222 // use a "su" suffix.
225 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
226 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
227 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
228 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
229 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
231 // Vector Rounding Shift.
232 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
233 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
234 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
236 // Vector Saturating Shift.
237 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
238 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
239 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
240 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
241 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
242 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
244 // Vector Saturating Rounding Shift.
245 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
246 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
247 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
248 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
249 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
251 // Vector Shift and Insert.
252 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
254 // Vector Absolute Value and Saturating Absolute Value.
255 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
256 def int_arm_neon_vabsf : Neon_1Arg_Float_Intrinsic;
257 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
259 // Vector Saturating Negate.
260 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
262 // Vector Count Leading Sign/Zero Bits.
263 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
264 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
266 // Vector Count One Bits.
267 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
269 // Vector Reciprocal Estimate.
270 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
271 def int_arm_neon_vrecpef : Neon_1Arg_Float_Intrinsic;
273 // Vector Reciprocal Square Root Estimate.
274 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
275 def int_arm_neon_vrsqrtef : Neon_1Arg_Float_Intrinsic;
277 // Vector Conversions Between Floating-point and Fixed-point.
278 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
279 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
280 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
281 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
283 // Narrowing and Lengthening Vector Moves.
284 def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic;
285 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
286 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
287 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
288 def int_arm_neon_vmovls : Neon_1Arg_Long_Intrinsic;
289 def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic;
291 let TargetPrefix = "arm" in {
293 // De-interleaving vector loads from N-element structures.
294 def int_arm_neon_vldi : Intrinsic<[llvm_anyint_ty],
295 [llvm_ptr_ty, llvm_i32_ty],
297 def int_arm_neon_vldf : Intrinsic<[llvm_anyfloat_ty],
298 [llvm_ptr_ty, llvm_i32_ty],
301 // Interleaving vector stores from N-element structures.
302 def int_arm_neon_vsti : Intrinsic<[llvm_void_ty],
303 [llvm_ptr_ty, llvm_anyint_ty, llvm_i32_ty],
305 def int_arm_neon_vstf : Intrinsic<[llvm_void_ty],
306 [llvm_ptr_ty, llvm_anyfloat_ty,llvm_i32_ty],
309 // Vector Table Lookup
310 def int_arm_neon_vtbl : Intrinsic<[llvm_v8i8_ty],
311 [llvm_anyint_ty, llvm_v8i8_ty],
313 // Vector Table Extension
314 def int_arm_neon_vtbx : Intrinsic<[llvm_v8i8_ty],
315 [llvm_v8i8_ty, llvm_anyint_ty,
316 llvm_v8i8_ty], [IntrNoMem]>;