1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
27 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
28 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
29 [IntrNoMem, Commutative]>;
30 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
31 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
32 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
33 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
34 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
35 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
38 //===----------------------------------------------------------------------===//
39 // Load and Store exclusive doubleword
41 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
42 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
43 llvm_ptr_ty], [IntrReadWriteArgMem]>;
44 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty],
48 //===----------------------------------------------------------------------===//
51 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
52 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
53 Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
54 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
55 Intrinsic<[], [llvm_i32_ty], []>;
56 def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
58 def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
62 //===----------------------------------------------------------------------===//
65 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
66 // Move to coprocessor
67 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
68 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
69 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
70 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
71 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
72 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
74 // Move from coprocessor
75 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
76 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
77 llvm_i32_ty, llvm_i32_ty], []>;
78 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
79 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
80 llvm_i32_ty, llvm_i32_ty], []>;
82 // Coprocessor data processing
83 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
84 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
85 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
86 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
87 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
88 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
90 // Move from two registers to coprocessor
91 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
92 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
93 llvm_i32_ty, llvm_i32_ty], []>;
94 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
95 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
96 llvm_i32_ty, llvm_i32_ty], []>;
99 //===----------------------------------------------------------------------===//
100 // Advanced SIMD (NEON)
102 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
104 // The following classes do not correspond directly to GCC builtins.
105 class Neon_1Arg_Intrinsic
106 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
107 class Neon_1Arg_Narrow_Intrinsic
108 : Intrinsic<[llvm_anyvector_ty],
109 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
110 class Neon_2Arg_Intrinsic
111 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
113 class Neon_2Arg_Narrow_Intrinsic
114 : Intrinsic<[llvm_anyvector_ty],
115 [LLVMExtendedElementVectorType<0>,
116 LLVMExtendedElementVectorType<0>],
118 class Neon_2Arg_Long_Intrinsic
119 : Intrinsic<[llvm_anyvector_ty],
120 [LLVMTruncatedElementVectorType<0>,
121 LLVMTruncatedElementVectorType<0>],
123 class Neon_3Arg_Intrinsic
124 : Intrinsic<[llvm_anyvector_ty],
125 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
127 class Neon_3Arg_Long_Intrinsic
128 : Intrinsic<[llvm_anyvector_ty],
130 LLVMTruncatedElementVectorType<0>,
131 LLVMTruncatedElementVectorType<0>],
133 class Neon_CvtFxToFP_Intrinsic
134 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
135 class Neon_CvtFPToFx_Intrinsic
136 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
138 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
139 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
140 // Overall, the classes range from 2 to 6 v8i8 arguments.
141 class Neon_Tbl2Arg_Intrinsic
142 : Intrinsic<[llvm_v8i8_ty],
143 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
144 class Neon_Tbl3Arg_Intrinsic
145 : Intrinsic<[llvm_v8i8_ty],
146 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
147 class Neon_Tbl4Arg_Intrinsic
148 : Intrinsic<[llvm_v8i8_ty],
149 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
151 class Neon_Tbl5Arg_Intrinsic
152 : Intrinsic<[llvm_v8i8_ty],
153 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
154 llvm_v8i8_ty], [IntrNoMem]>;
155 class Neon_Tbl6Arg_Intrinsic
156 : Intrinsic<[llvm_v8i8_ty],
157 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
158 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
163 let Properties = [IntrNoMem, Commutative] in {
166 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
167 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
168 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
169 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
170 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
171 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
172 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
173 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
176 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
177 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
178 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
179 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
180 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
181 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
182 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
184 // Vector Multiply and Accumulate/Subtract.
185 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
186 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
189 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
190 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
193 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
194 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
196 // Vector Reciprocal Step.
197 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
199 // Vector Reciprocal Square Root Step.
200 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
204 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
205 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
206 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
207 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
208 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
209 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
211 // Vector Absolute Compare.
212 let TargetPrefix = "arm" in {
213 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
214 [llvm_v2f32_ty, llvm_v2f32_ty],
216 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
217 [llvm_v4f32_ty, llvm_v4f32_ty],
219 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
220 [llvm_v2f32_ty, llvm_v2f32_ty],
222 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
223 [llvm_v4f32_ty, llvm_v4f32_ty],
227 // Vector Absolute Differences.
228 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
229 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
231 // Vector Pairwise Add.
232 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
234 // Vector Pairwise Add Long.
235 // Note: This is different than the other "long" NEON intrinsics because
236 // the result vector has half as many elements as the source vector.
237 // The source and destination vector types must be specified separately.
238 let TargetPrefix = "arm" in {
239 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
241 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
245 // Vector Pairwise Add and Accumulate Long.
246 // Note: This is similar to vpaddl but the destination vector also appears
247 // as the first argument.
248 let TargetPrefix = "arm" in {
249 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
250 [LLVMMatchType<0>, llvm_anyvector_ty],
252 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
253 [LLVMMatchType<0>, llvm_anyvector_ty],
257 // Vector Pairwise Maximum and Minimum.
258 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
259 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
260 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
261 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
265 // The various saturating and rounding vector shift operations need to be
266 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
267 // operation cannot be safely translated to LLVM's shift operators. VSHL can
268 // be used for both left and right shifts, or even combinations of the two,
269 // depending on the signs of the shift amounts. It also has well-defined
270 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
271 // by constants can be represented with LLVM's shift operators.
273 // The shift counts for these intrinsics are always vectors, even for constant
274 // shifts, where the constant is replicated. For consistency with VSHL (and
275 // other variable shift instructions), left shifts have positive shift counts
276 // and right shifts have negative shift counts. This convention is also used
277 // for constant right shift intrinsics, and to help preserve sanity, the
278 // intrinsic names use "shift" instead of either "shl" or "shr". Where
279 // applicable, signed and unsigned versions of the intrinsics are
280 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
281 // such as VQSHLU, take signed operands but produce unsigned results; these
282 // use a "su" suffix.
285 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
286 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
287 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
288 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
289 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
291 // Vector Rounding Shift.
292 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
293 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
294 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
296 // Vector Saturating Shift.
297 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
298 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
299 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
300 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
301 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
302 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
304 // Vector Saturating Rounding Shift.
305 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
306 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
307 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
308 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
309 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
311 // Vector Shift and Insert.
312 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
314 // Vector Absolute Value and Saturating Absolute Value.
315 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
316 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
318 // Vector Saturating Negate.
319 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
321 // Vector Count Leading Sign/Zero Bits.
322 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
323 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
325 // Vector Count One Bits.
326 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
328 // Vector Reciprocal Estimate.
329 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
331 // Vector Reciprocal Square Root Estimate.
332 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
334 // Vector Conversions Between Floating-point and Fixed-point.
335 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
336 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
337 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
338 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
340 // Vector Conversions Between Half-Precision and Single-Precision.
341 def int_arm_neon_vcvtfp2hf
342 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
343 def int_arm_neon_vcvthf2fp
344 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
346 // Narrowing Saturating Vector Moves.
347 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
348 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
349 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
351 // Vector Table Lookup.
352 // The first 1-4 arguments are the table.
353 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
354 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
355 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
356 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
358 // Vector Table Extension.
359 // Some elements of the destination vector may not be updated, so the original
360 // value of that vector is passed as the first argument. The next 1-4
361 // arguments after that are the table.
362 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
363 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
364 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
365 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
367 let TargetPrefix = "arm" in {
369 // De-interleaving vector loads from N-element structures.
370 // Source operands are the address and alignment.
371 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
372 [llvm_ptr_ty, llvm_i32_ty],
374 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
375 [llvm_ptr_ty, llvm_i32_ty],
377 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
379 [llvm_ptr_ty, llvm_i32_ty],
381 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
382 LLVMMatchType<0>, LLVMMatchType<0>],
383 [llvm_ptr_ty, llvm_i32_ty],
386 // Vector load N-element structure to one lane.
387 // Source operands are: the address, the N input vectors (since only one
388 // lane is assigned), the lane number, and the alignment.
389 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
390 [llvm_ptr_ty, LLVMMatchType<0>,
391 LLVMMatchType<0>, llvm_i32_ty,
392 llvm_i32_ty], [IntrReadArgMem]>;
393 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
395 [llvm_ptr_ty, LLVMMatchType<0>,
396 LLVMMatchType<0>, LLVMMatchType<0>,
397 llvm_i32_ty, llvm_i32_ty],
399 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
400 LLVMMatchType<0>, LLVMMatchType<0>],
401 [llvm_ptr_ty, LLVMMatchType<0>,
402 LLVMMatchType<0>, LLVMMatchType<0>,
403 LLVMMatchType<0>, llvm_i32_ty,
404 llvm_i32_ty], [IntrReadArgMem]>;
406 // Interleaving vector stores from N-element structures.
407 // Source operands are: the address, the N vectors, and the alignment.
408 def int_arm_neon_vst1 : Intrinsic<[],
409 [llvm_ptr_ty, llvm_anyvector_ty,
410 llvm_i32_ty], [IntrReadWriteArgMem]>;
411 def int_arm_neon_vst2 : Intrinsic<[],
412 [llvm_ptr_ty, llvm_anyvector_ty,
413 LLVMMatchType<0>, llvm_i32_ty],
414 [IntrReadWriteArgMem]>;
415 def int_arm_neon_vst3 : Intrinsic<[],
416 [llvm_ptr_ty, llvm_anyvector_ty,
417 LLVMMatchType<0>, LLVMMatchType<0>,
418 llvm_i32_ty], [IntrReadWriteArgMem]>;
419 def int_arm_neon_vst4 : Intrinsic<[],
420 [llvm_ptr_ty, llvm_anyvector_ty,
421 LLVMMatchType<0>, LLVMMatchType<0>,
422 LLVMMatchType<0>, llvm_i32_ty],
423 [IntrReadWriteArgMem]>;
425 // Vector store N-element structure from one lane.
426 // Source operands are: the address, the N vectors, the lane number, and
428 def int_arm_neon_vst2lane : Intrinsic<[],
429 [llvm_ptr_ty, llvm_anyvector_ty,
430 LLVMMatchType<0>, llvm_i32_ty,
431 llvm_i32_ty], [IntrReadWriteArgMem]>;
432 def int_arm_neon_vst3lane : Intrinsic<[],
433 [llvm_ptr_ty, llvm_anyvector_ty,
434 LLVMMatchType<0>, LLVMMatchType<0>,
435 llvm_i32_ty, llvm_i32_ty],
436 [IntrReadWriteArgMem]>;
437 def int_arm_neon_vst4lane : Intrinsic<[],
438 [llvm_ptr_ty, llvm_anyvector_ty,
439 LLVMMatchType<0>, LLVMMatchType<0>,
440 LLVMMatchType<0>, llvm_i32_ty,
441 llvm_i32_ty], [IntrReadWriteArgMem]>;