1 //===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MCInst and MCOperand classes, which
11 // is the basic representation used to represent low-level machine code
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCINST_H
17 #define LLVM_MC_MCINST_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/Support/DataTypes.h"
27 /// MCOperand - Instances of this class represent operands of the MCInst class.
28 /// This is a simple discriminated union.
30 enum MachineOperandType {
31 kInvalid, ///< Uninitialized.
32 kRegister, ///< Register operand.
33 kImmediate, ///< Immediate operand.
34 kExpr ///< Relocatable immediate operand.
41 const MCExpr *ExprVal;
45 MCOperand() : Kind(kInvalid) {}
46 MCOperand(const MCOperand &RHS) { *this = RHS; }
48 bool isValid() const { return Kind != kInvalid; }
49 bool isReg() const { return Kind == kRegister; }
50 bool isImm() const { return Kind == kImmediate; }
51 bool isExpr() const { return Kind == kExpr; }
53 /// getReg - Returns the register number.
54 unsigned getReg() const {
55 assert(isReg() && "This is not a register operand!");
59 /// setReg - Set the register number.
60 void setReg(unsigned Reg) {
61 assert(isReg() && "This is not a register operand!");
65 int64_t getImm() const {
66 assert(isImm() && "This is not an immediate");
69 void setImm(int64_t Val) {
70 assert(isImm() && "This is not an immediate");
74 const MCExpr *getExpr() const {
75 assert(isExpr() && "This is not an expression");
78 void setExpr(const MCExpr *Val) {
79 assert(isExpr() && "This is not an expression");
83 static MCOperand CreateReg(unsigned Reg) {
89 static MCOperand CreateImm(int64_t Val) {
95 static MCOperand CreateExpr(const MCExpr *Val) {
102 void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
107 /// MCInst - Instances of this class represent a single low-level machine
111 SmallVector<MCOperand, 8> Operands;
113 MCInst() : Opcode(0) {}
115 void setOpcode(unsigned Op) { Opcode = Op; }
117 unsigned getOpcode() const { return Opcode; }
119 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
120 MCOperand &getOperand(unsigned i) { return Operands[i]; }
121 unsigned getNumOperands() const { return Operands.size(); }
123 void addOperand(const MCOperand &Op) {
124 Operands.push_back(Op);
127 void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
132 } // end namespace llvm