1 //===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MCInst and MCOperand classes, which
11 // is the basic representation used to represent low-level machine code
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCINST_H
17 #define LLVM_MC_MCINST_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/System/DataTypes.h"
29 /// MCOperand - Instances of this class represent operands of the MCInst class.
30 /// This is a simple discriminated union.
32 enum MachineOperandType {
33 kInvalid, ///< Uninitialized.
34 kRegister, ///< Register operand.
35 kImmediate, ///< Immediate operand.
36 kExpr ///< Relocatable immediate operand.
43 const MCExpr *ExprVal;
47 MCOperand() : Kind(kInvalid) {}
49 bool isValid() const { return Kind != kInvalid; }
50 bool isReg() const { return Kind == kRegister; }
51 bool isImm() const { return Kind == kImmediate; }
52 bool isExpr() const { return Kind == kExpr; }
54 /// getReg - Returns the register number.
55 unsigned getReg() const {
56 assert(isReg() && "This is not a register operand!");
60 /// setReg - Set the register number.
61 void setReg(unsigned Reg) {
62 assert(isReg() && "This is not a register operand!");
66 int64_t getImm() const {
67 assert(isImm() && "This is not an immediate");
70 void setImm(int64_t Val) {
71 assert(isImm() && "This is not an immediate");
75 const MCExpr *getExpr() const {
76 assert(isExpr() && "This is not an expression");
79 void setExpr(const MCExpr *Val) {
80 assert(isExpr() && "This is not an expression");
84 static MCOperand CreateReg(unsigned Reg) {
90 static MCOperand CreateImm(int64_t Val) {
96 static MCOperand CreateExpr(const MCExpr *Val) {
103 void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
108 /// MCInst - Instances of this class represent a single low-level machine
112 SmallVector<MCOperand, 8> Operands;
114 MCInst() : Opcode(0) {}
116 void setOpcode(unsigned Op) { Opcode = Op; }
118 unsigned getOpcode() const { return Opcode; }
120 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
121 MCOperand &getOperand(unsigned i) { return Operands[i]; }
122 unsigned getNumOperands() const { return Operands.size(); }
124 void addOperand(const MCOperand &Op) {
125 Operands.push_back(Op);
128 void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
131 /// \brief Dump the MCInst as prettily as possible using the additional MC
132 /// structures, if given. Operators are separated by the \arg Separator
134 void dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI = 0,
135 const MCInstPrinter *Printer = 0,
136 StringRef Separator = " ") const;
140 } // end namespace llvm