1 //===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MCInst and MCOperand classes, which
11 // is the basic representation used to represent low-level machine code
14 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_MC_MCINST_H
18 #define LLVM_MC_MCINST_H
20 #include "llvm/ADT/SmallVector.h"
24 /// MCOperand - Instances of this class represent operands of the MCInst class.
25 /// This is a simple discriminated union.
27 enum MachineOperandType {
28 kInvalid, ///< Uninitialized.
29 kRegister, ///< Register operand.
30 kImmediate ///< Immediate operand.
40 MCOperand() : Kind(kInvalid) {}
41 MCOperand(const MCOperand &RHS) { *this = RHS; }
43 bool isReg() const { return Kind == kRegister; }
44 bool isImm() const { return Kind == kImmediate; }
46 /// getReg - Returns the register number.
47 unsigned getReg() const {
48 assert(isReg() && "This is not a register operand!");
52 /// setReg - Set the register number.
53 void setReg(unsigned Reg) {
54 assert(isReg() && "This is not a register operand!");
58 uint64_t getImm() const {
59 assert(isImm() && "This is not an immediate");
62 void setImm(uint64_t Val) {
63 assert(isImm() && "This is not an immediate");
67 void MakeReg(unsigned Reg) {
71 void MakeImm(uint64_t Val) {
78 /// MCInst - Instances of this class represent a single low-level machine
82 SmallVector<MCOperand, 8> Operands;
84 MCInst() : Opcode(~0U) {}
91 } // end namespace llvm