1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/Support/DataTypes.h"
22 //===----------------------------------------------------------------------===//
23 // Machine Operand Flags and Description
24 //===----------------------------------------------------------------------===//
27 // Operand constraints
28 enum OperandConstraint {
29 TIED_TO = 0, // Must be allocated the same register as.
30 EARLY_CLOBBER // Operand is an early clobber register operand
33 /// OperandFlags - These are flags set on operands, but should be considered
34 /// private, all access should go through the MCOperandInfo accessors.
35 /// See the accessors for a description of what these are.
37 LookupPtrRegClass = 0,
42 /// Operand Type - Operands are tagged with one of the values of this enum.
52 /// MCOperandInfo - This holds information about one operand of a machine
53 /// instruction, indicating the register class for register operands, etc.
57 /// RegClass - This specifies the register class enumeration of the operand
58 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
59 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60 /// get a dynamic register class.
63 /// Flags - These are flags from the MCOI::OperandFlags enum.
66 /// OperandType - Information about the type of the operand.
69 /// Lower 16 bits are used to specify which constraints are set. The higher 16
70 /// bits are used to specify the value of constraints (4 bits each).
72 /// Currently no other information.
74 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75 /// requires a callback to look up its register class.
76 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
78 /// isPredicate - Set if this is one of the operands that made up of
79 /// the predicate operand that controls an isPredicable() instruction.
80 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
82 /// isOptionalDef - Set if this operand is a optional def.
84 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
88 //===----------------------------------------------------------------------===//
89 // Machine Instruction Flags and Description
90 //===----------------------------------------------------------------------===//
92 /// MCInstrDesc flags - These should be considered private to the
93 /// implementation of the MCInstrDesc class. Clients should use the predicate
94 /// methods on MCInstrDesc, not use these directly. These all correspond to
95 /// bitfields in the MCInstrDesc::Flags field.
117 UnmodeledSideEffects,
129 /// MCInstrDesc - Describe properties that are true of each instruction in the
130 /// target description file. This captures information about side effects,
131 /// register use and many other things. There is one instance of this struct
132 /// for each target instruction class, and the MachineInstr class points to
133 /// this struct directly to describe itself.
136 unsigned short Opcode; // The opcode number
137 unsigned short NumOperands; // Num of args (may be more if variable_ops)
138 unsigned short NumDefs; // Num of args that are definitions
139 unsigned short SchedClass; // enum identifying instr sched class
140 unsigned short Size; // Number of bytes in encoding.
141 unsigned Flags; // Flags identifying machine instr class
142 uint64_t TSFlags; // Target Specific Flag values
143 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
144 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
145 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
147 /// getOperandConstraint - Returns the value of the specific constraint if
148 /// it is set. Returns -1 if it is not set.
149 int getOperandConstraint(unsigned OpNum,
150 MCOI::OperandConstraint Constraint) const {
151 if (OpNum < NumOperands &&
152 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
153 unsigned Pos = 16 + Constraint * 4;
154 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
159 /// getOpcode - Return the opcode number for this descriptor.
160 unsigned getOpcode() const {
164 /// getNumOperands - Return the number of declared MachineOperands for this
165 /// MachineInstruction. Note that variadic (isVariadic() returns true)
166 /// instructions may have additional operands at the end of the list, and note
167 /// that the machine instruction may include implicit register def/uses as
169 unsigned getNumOperands() const {
173 /// getNumDefs - Return the number of MachineOperands that are register
174 /// definitions. Register definitions always occur at the start of the
175 /// machine operand list. This is the number of "outs" in the .td file,
176 /// and does not include implicit defs.
177 unsigned getNumDefs() const {
181 /// getFlags - Return flags of this instruction.
183 unsigned getFlags() const { return Flags; }
185 /// isVariadic - Return true if this instruction can have a variable number of
186 /// operands. In this case, the variable operands will be after the normal
187 /// operands but before the implicit definitions and uses (if any are
189 bool isVariadic() const {
190 return Flags & (1 << MCID::Variadic);
193 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
194 /// ARM instructions which can set condition code if 's' bit is set.
195 bool hasOptionalDef() const {
196 return Flags & (1 << MCID::HasOptionalDef);
199 /// isPseudo - Return true if this is a pseudo instruction that doesn't
200 /// correspond to a real machine instruction.
202 bool isPseudo() const {
203 return Flags & (1 << MCID::Pseudo);
206 bool isReturn() const {
207 return Flags & (1 << MCID::Return);
210 bool isCall() const {
211 return Flags & (1 << MCID::Call);
214 /// isBarrier - Returns true if the specified instruction stops control flow
215 /// from executing the instruction immediately following it. Examples include
216 /// unconditional branches and return instructions.
217 bool isBarrier() const {
218 return Flags & (1 << MCID::Barrier);
221 /// isTerminator - Returns true if this instruction part of the terminator for
222 /// a basic block. Typically this is things like return and branch
225 /// Various passes use this to insert code into the bottom of a basic block,
226 /// but before control flow occurs.
227 bool isTerminator() const {
228 return Flags & (1 << MCID::Terminator);
231 /// isBranch - Returns true if this is a conditional, unconditional, or
232 /// indirect branch. Predicates below can be used to discriminate between
233 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
234 /// get more information.
235 bool isBranch() const {
236 return Flags & (1 << MCID::Branch);
239 /// isIndirectBranch - Return true if this is an indirect branch, such as a
240 /// branch through a register.
241 bool isIndirectBranch() const {
242 return Flags & (1 << MCID::IndirectBranch);
245 /// isConditionalBranch - Return true if this is a branch which may fall
246 /// through to the next instruction or may transfer control flow to some other
247 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
248 /// information about this branch.
249 bool isConditionalBranch() const {
250 return isBranch() & !isBarrier() & !isIndirectBranch();
253 /// isUnconditionalBranch - Return true if this is a branch which always
254 /// transfers control flow to some other block. The
255 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
256 /// about this branch.
257 bool isUnconditionalBranch() const {
258 return isBranch() & isBarrier() & !isIndirectBranch();
261 // isPredicable - Return true if this instruction has a predicate operand that
262 // controls execution. It may be set to 'always', or may be set to other
263 /// values. There are various methods in TargetInstrInfo that can be used to
264 /// control and modify the predicate in this instruction.
265 bool isPredicable() const {
266 return Flags & (1 << MCID::Predicable);
269 /// isCompare - Return true if this instruction is a comparison.
270 bool isCompare() const {
271 return Flags & (1 << MCID::Compare);
274 /// isMoveImmediate - Return true if this instruction is a move immediate
275 /// (including conditional moves) instruction.
276 bool isMoveImmediate() const {
277 return Flags & (1 << MCID::MoveImm);
280 /// isBitcast - Return true if this instruction is a bitcast instruction.
282 bool isBitcast() const {
283 return Flags & (1 << MCID::Bitcast);
286 /// isSelect - Return true if this is a select instruction.
288 bool isSelect() const {
289 return Flags & (1 << MCID::Select);
292 /// isNotDuplicable - Return true if this instruction cannot be safely
293 /// duplicated. For example, if the instruction has a unique labels attached
294 /// to it, duplicating it would cause multiple definition errors.
295 bool isNotDuplicable() const {
296 return Flags & (1 << MCID::NotDuplicable);
299 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
300 /// which must be filled by the code generator.
301 bool hasDelaySlot() const {
302 return Flags & (1 << MCID::DelaySlot);
305 /// canFoldAsLoad - Return true for instructions that can be folded as
306 /// memory operands in other instructions. The most common use for this
307 /// is instructions that are simple loads from memory that don't modify
308 /// the loaded value in any way, but it can also be used for instructions
309 /// that can be expressed as constant-pool loads, such as V_SETALLONES
310 /// on x86, to allow them to be folded when it is beneficial.
311 /// This should only be set on instructions that return a value in their
312 /// only virtual register definition.
313 bool canFoldAsLoad() const {
314 return Flags & (1 << MCID::FoldableAsLoad);
317 //===--------------------------------------------------------------------===//
318 // Side Effect Analysis
319 //===--------------------------------------------------------------------===//
321 /// mayLoad - Return true if this instruction could possibly read memory.
322 /// Instructions with this flag set are not necessarily simple load
323 /// instructions, they may load a value and modify it, for example.
324 bool mayLoad() const {
325 return Flags & (1 << MCID::MayLoad);
329 /// mayStore - Return true if this instruction could possibly modify memory.
330 /// Instructions with this flag set are not necessarily simple store
331 /// instructions, they may store a modified value based on their operands, or
332 /// may not actually modify anything, for example.
333 bool mayStore() const {
334 return Flags & (1 << MCID::MayStore);
337 /// hasUnmodeledSideEffects - Return true if this instruction has side
338 /// effects that are not modeled by other flags. This does not return true
339 /// for instructions whose effects are captured by:
341 /// 1. Their operand list and implicit definition/use list. Register use/def
342 /// info is explicit for instructions.
343 /// 2. Memory accesses. Use mayLoad/mayStore.
344 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
346 /// Examples of side effects would be modifying 'invisible' machine state like
347 /// a control register, flushing a cache, modifying a register invisible to
350 bool hasUnmodeledSideEffects() const {
351 return Flags & (1 << MCID::UnmodeledSideEffects);
354 //===--------------------------------------------------------------------===//
355 // Flags that indicate whether an instruction can be modified by a method.
356 //===--------------------------------------------------------------------===//
358 /// isCommutable - Return true if this may be a 2- or 3-address
359 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
360 /// result if Y and Z are exchanged. If this flag is set, then the
361 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
364 /// Note that this flag may be set on instructions that are only commutable
365 /// sometimes. In these cases, the call to commuteInstruction will fail.
366 /// Also note that some instructions require non-trivial modification to
368 bool isCommutable() const {
369 return Flags & (1 << MCID::Commutable);
372 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
373 /// which can be changed into a 3-address instruction if needed. Doing this
374 /// transformation can be profitable in the register allocator, because it
375 /// means that the instruction can use a 2-address form if possible, but
376 /// degrade into a less efficient form if the source and dest register cannot
377 /// be assigned to the same register. For example, this allows the x86
378 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
379 /// is the same speed as the shift but has bigger code size.
381 /// If this returns true, then the target must implement the
382 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
383 /// is allowed to fail if the transformation isn't valid for this specific
384 /// instruction (e.g. shl reg, 4 on x86).
386 bool isConvertibleTo3Addr() const {
387 return Flags & (1 << MCID::ConvertibleTo3Addr);
390 /// usesCustomInsertionHook - Return true if this instruction requires
391 /// custom insertion support when the DAG scheduler is inserting it into a
392 /// machine basic block. If this is true for the instruction, it basically
393 /// means that it is a pseudo instruction used at SelectionDAG time that is
394 /// expanded out into magic code by the target when MachineInstrs are formed.
396 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
397 /// is used to insert this into the MachineBasicBlock.
398 bool usesCustomInsertionHook() const {
399 return Flags & (1 << MCID::UsesCustomInserter);
402 /// hasPostISelHook - Return true if this instruction requires *adjustment*
403 /// after instruction selection by calling a target hook. For example, this
404 /// can be used to fill in ARM 's' optional operand depending on whether
405 /// the conditional flag register is used.
406 bool hasPostISelHook() const {
407 return Flags & (1 << MCID::HasPostISelHook);
410 /// isRematerializable - Returns true if this instruction is a candidate for
411 /// remat. This flag is deprecated, please don't use it anymore. If this
412 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
413 /// verify the instruction is really rematable.
414 bool isRematerializable() const {
415 return Flags & (1 << MCID::Rematerializable);
418 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
419 /// less) than a move instruction. This is useful during certain types of
420 /// optimizations (e.g., remat during two-address conversion or machine licm)
421 /// where we would like to remat or hoist the instruction, but not if it costs
422 /// more than moving the instruction into the appropriate register. Note, we
423 /// are not marking copies from and to the same register class with this flag.
424 bool isAsCheapAsAMove() const {
425 return Flags & (1 << MCID::CheapAsAMove);
428 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
429 /// have special register allocation requirements that are not captured by the
430 /// operand register classes. e.g. ARM::STRD's two source registers must be an
431 /// even / odd pair, ARM::STM registers have to be in ascending order.
432 /// Post-register allocation passes should not attempt to change allocations
433 /// for sources of instructions with this flag.
434 bool hasExtraSrcRegAllocReq() const {
435 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
438 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
439 /// have special register allocation requirements that are not captured by the
440 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
441 /// even / odd pair, ARM::LDM registers have to be in ascending order.
442 /// Post-register allocation passes should not attempt to change allocations
443 /// for definitions of instructions with this flag.
444 bool hasExtraDefRegAllocReq() const {
445 return Flags & (1 << MCID::ExtraDefRegAllocReq);
449 /// getImplicitUses - Return a list of registers that are potentially
450 /// read by any instance of this machine instruction. For example, on X86,
451 /// the "adc" instruction adds two register operands and adds the carry bit in
452 /// from the flags register. In this case, the instruction is marked as
453 /// implicitly reading the flags. Likewise, the variable shift instruction on
454 /// X86 is marked as implicitly reading the 'CL' register, which it always
457 /// This method returns null if the instruction has no implicit uses.
458 const uint16_t *getImplicitUses() const {
462 /// getNumImplicitUses - Return the number of implicit uses this instruction
464 unsigned getNumImplicitUses() const {
465 if (ImplicitUses == 0) return 0;
467 for (; ImplicitUses[i]; ++i) /*empty*/;
471 /// getImplicitDefs - Return a list of registers that are potentially
472 /// written by any instance of this machine instruction. For example, on X86,
473 /// many instructions implicitly set the flags register. In this case, they
474 /// are marked as setting the FLAGS. Likewise, many instructions always
475 /// deposit their result in a physical register. For example, the X86 divide
476 /// instruction always deposits the quotient and remainder in the EAX/EDX
477 /// registers. For that instruction, this will return a list containing the
478 /// EAX/EDX/EFLAGS registers.
480 /// This method returns null if the instruction has no implicit defs.
481 const uint16_t *getImplicitDefs() const {
485 /// getNumImplicitDefs - Return the number of implicit defs this instruction
487 unsigned getNumImplicitDefs() const {
488 if (ImplicitDefs == 0) return 0;
490 for (; ImplicitDefs[i]; ++i) /*empty*/;
494 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
495 /// uses the specified physical register.
496 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
497 if (const uint16_t *ImpUses = ImplicitUses)
498 for (; *ImpUses; ++ImpUses)
499 if (*ImpUses == Reg) return true;
503 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
504 /// defines the specified physical register.
505 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
506 if (const uint16_t *ImpDefs = ImplicitDefs)
507 for (; *ImpDefs; ++ImpDefs)
508 if (*ImpDefs == Reg) return true;
512 /// getSchedClass - Return the scheduling class for this instruction. The
513 /// scheduling class is an index into the InstrItineraryData table. This
514 /// returns zero if there is no known scheduling information for the
517 unsigned getSchedClass() const {
521 /// getSize - Return the number of bytes in the encoding of this instruction,
522 /// or zero if the encoding size cannot be known from the opcode.
523 unsigned getSize() const {
527 /// findFirstPredOperandIdx() - Find the index of the first operand in the
528 /// operand list that is used to represent the predicate. It returns -1 if
530 int findFirstPredOperandIdx() const {
531 if (isPredicable()) {
532 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
533 if (OpInfo[i].isPredicate())
540 } // end namespace llvm