1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/Support/DataTypes.h"
24 class MCSubtargetInfo;
26 //===----------------------------------------------------------------------===//
27 // Machine Operand Flags and Description
28 //===----------------------------------------------------------------------===//
31 // Operand constraints
32 enum OperandConstraint {
33 TIED_TO = 0, // Must be allocated the same register as.
34 EARLY_CLOBBER // Operand is an early clobber register operand
37 /// \brief These are flags set on operands, but should be considered
38 /// private, all access should go through the MCOperandInfo accessors.
39 /// See the accessors for a description of what these are.
40 enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef };
42 /// \brief Operands are tagged with one of the values of this enum.
45 OPERAND_IMMEDIATE = 1,
49 OPERAND_FIRST_TARGET = 5
53 /// \brief This holds information about one operand of a machine instruction,
54 /// indicating the register class for register operands, etc.
57 /// \brief This specifies the register class enumeration of the operand
58 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
59 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60 /// get a dynamic register class.
63 /// \brief These are flags from the MCOI::OperandFlags enum.
66 /// \brief Information about the type of the operand.
68 /// \brief The lower 16 bits are used to specify which constraints are set.
69 /// The higher 16 bits are used to specify the value of constraints (4 bits
73 /// \brief Set if this operand is a pointer value and it requires a callback
74 /// to look up its register class.
75 bool isLookupPtrRegClass() const {
76 return Flags & (1 << MCOI::LookupPtrRegClass);
79 /// \brief Set if this is one of the operands that made up of the predicate
80 /// operand that controls an isPredicable() instruction.
81 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
83 /// \brief Set if this operand is a optional def.
84 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
87 //===----------------------------------------------------------------------===//
88 // Machine Instruction Flags and Description
89 //===----------------------------------------------------------------------===//
92 /// \brief These should be considered private to the implementation of the
93 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
94 /// not use these directly. These all correspond to bitfields in the
95 /// MCInstrDesc::Flags field.
116 UnmodeledSideEffects,
131 /// \brief Describe properties that are true of each instruction in the target
132 /// description file. This captures information about side effects, register
133 /// use and many other things. There is one instance of this struct for each
134 /// target instruction class, and the MachineInstr class points to this struct
135 /// directly to describe itself.
138 unsigned short Opcode; // The opcode number
139 unsigned short NumOperands; // Num of args (may be more if variable_ops)
140 unsigned short NumDefs; // Num of args that are definitions
141 unsigned short SchedClass; // enum identifying instr sched class
142 unsigned short Size; // Number of bytes in encoding.
143 unsigned Flags; // Flags identifying machine instr class
144 uint64_t TSFlags; // Target Specific Flag values
145 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
146 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
147 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
149 DeprecatedFeatureMask; // Feature bits that this is deprecated on, if any
150 // A complex method to determine is a certain is deprecated or not, and return
151 // the reason for deprecation.
152 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
154 /// \brief Returns the value of the specific constraint if
155 /// it is set. Returns -1 if it is not set.
156 int getOperandConstraint(unsigned OpNum,
157 MCOI::OperandConstraint Constraint) const {
158 if (OpNum < NumOperands &&
159 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
160 unsigned Pos = 16 + Constraint * 4;
161 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
166 /// \brief Returns true if a certain instruction is deprecated and if so
167 /// returns the reason in \p Info.
168 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
169 std::string &Info) const;
171 /// \brief Return the opcode number for this descriptor.
172 unsigned getOpcode() const { return Opcode; }
174 /// \brief Return the number of declared MachineOperands for this
175 /// MachineInstruction. Note that variadic (isVariadic() returns true)
176 /// instructions may have additional operands at the end of the list, and note
177 /// that the machine instruction may include implicit register def/uses as
179 unsigned getNumOperands() const { return NumOperands; }
181 /// \brief Return the number of MachineOperands that are register
182 /// definitions. Register definitions always occur at the start of the
183 /// machine operand list. This is the number of "outs" in the .td file,
184 /// and does not include implicit defs.
185 unsigned getNumDefs() const { return NumDefs; }
187 /// \brief Return flags of this instruction.
188 unsigned getFlags() const { return Flags; }
190 /// \brief Return true if this instruction can have a variable number of
191 /// operands. In this case, the variable operands will be after the normal
192 /// operands but before the implicit definitions and uses (if any are
194 bool isVariadic() const { return Flags & (1 << MCID::Variadic); }
196 /// \brief Set if this instruction has an optional definition, e.g.
197 /// ARM instructions which can set condition code if 's' bit is set.
198 bool hasOptionalDef() const { return Flags & (1 << MCID::HasOptionalDef); }
200 /// \brief Return true if this is a pseudo instruction that doesn't
201 /// correspond to a real machine instruction.
202 bool isPseudo() const { return Flags & (1 << MCID::Pseudo); }
204 /// \brief Return true if the instruction is a return.
205 bool isReturn() const { return Flags & (1 << MCID::Return); }
207 /// \brief Return true if the instruction is a call.
208 bool isCall() const { return Flags & (1 << MCID::Call); }
210 /// \brief Returns true if the specified instruction stops control flow
211 /// from executing the instruction immediately following it. Examples include
212 /// unconditional branches and return instructions.
213 bool isBarrier() const { return Flags & (1 << MCID::Barrier); }
215 /// \brief Returns true if this instruction part of the terminator for
216 /// a basic block. Typically this is things like return and branch
219 /// Various passes use this to insert code into the bottom of a basic block,
220 /// but before control flow occurs.
221 bool isTerminator() const { return Flags & (1 << MCID::Terminator); }
223 /// \brief Returns true if this is a conditional, unconditional, or
224 /// indirect branch. Predicates below can be used to discriminate between
225 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
226 /// get more information.
227 bool isBranch() const { return Flags & (1 << MCID::Branch); }
229 /// \brief Return true if this is an indirect branch, such as a
230 /// branch through a register.
231 bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch); }
233 /// \brief Return true if this is a branch which may fall
234 /// through to the next instruction or may transfer control flow to some other
235 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
236 /// information about this branch.
237 bool isConditionalBranch() const {
238 return isBranch() & !isBarrier() & !isIndirectBranch();
241 /// \brief Return true if this is a branch which always
242 /// transfers control flow to some other block. The
243 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
244 /// about this branch.
245 bool isUnconditionalBranch() const {
246 return isBranch() & isBarrier() & !isIndirectBranch();
249 /// \brief Return true if this is a branch or an instruction which directly
250 /// writes to the program counter. Considered 'may' affect rather than
251 /// 'does' affect as things like predication are not taken into account.
252 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
254 /// \brief Return true if this instruction has a predicate operand
255 /// that controls execution. It may be set to 'always', or may be set to other
256 /// values. There are various methods in TargetInstrInfo that can be used to
257 /// control and modify the predicate in this instruction.
258 bool isPredicable() const { return Flags & (1 << MCID::Predicable); }
260 /// \brief Return true if this instruction is a comparison.
261 bool isCompare() const { return Flags & (1 << MCID::Compare); }
263 /// \brief Return true if this instruction is a move immediate
264 /// (including conditional moves) instruction.
265 bool isMoveImmediate() const { return Flags & (1 << MCID::MoveImm); }
267 /// \brief Return true if this instruction is a bitcast instruction.
268 bool isBitcast() const { return Flags & (1 << MCID::Bitcast); }
270 /// \brief Return true if this is a select instruction.
271 bool isSelect() const { return Flags & (1 << MCID::Select); }
273 /// \brief Return true if this instruction cannot be safely
274 /// duplicated. For example, if the instruction has a unique labels attached
275 /// to it, duplicating it would cause multiple definition errors.
276 bool isNotDuplicable() const { return Flags & (1 << MCID::NotDuplicable); }
278 /// \brief Returns true if the specified instruction has a delay slot which
279 /// must be filled by the code generator.
280 bool hasDelaySlot() const { return Flags & (1 << MCID::DelaySlot); }
282 /// \brief Return true for instructions that can be folded as memory operands
283 /// in other instructions. The most common use for this is instructions that
284 /// are simple loads from memory that don't modify the loaded value in any
285 /// way, but it can also be used for instructions that can be expressed as
286 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
287 /// folded when it is beneficial. This should only be set on instructions
288 /// that return a value in their only virtual register definition.
289 bool canFoldAsLoad() const { return Flags & (1 << MCID::FoldableAsLoad); }
291 /// \brief Return true if this instruction behaves
292 /// the same way as the generic REG_SEQUENCE instructions.
294 /// dX VMOVDRR rY, rZ
296 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
298 /// Note that for the optimizers to be able to take advantage of
299 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
300 /// override accordingly.
301 bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); }
303 /// \brief Return true if this instruction behaves
304 /// the same way as the generic EXTRACT_SUBREG instructions.
306 /// rX, rY VMOVRRD dZ
307 /// is equivalent to two EXTRACT_SUBREG:
308 /// rX = EXTRACT_SUBREG dZ, ssub_0
309 /// rY = EXTRACT_SUBREG dZ, ssub_1
311 /// Note that for the optimizers to be able to take advantage of
312 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
313 /// override accordingly.
314 bool isExtractSubregLike() const {
315 return Flags & (1 << MCID::ExtractSubreg);
318 /// \brief Return true if this instruction behaves
319 /// the same way as the generic INSERT_SUBREG instructions.
321 /// dX = VSETLNi32 dY, rZ, Imm
322 /// is equivalent to a INSERT_SUBREG:
323 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
325 /// Note that for the optimizers to be able to take advantage of
326 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
327 /// override accordingly.
328 bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); }
330 //===--------------------------------------------------------------------===//
331 // Side Effect Analysis
332 //===--------------------------------------------------------------------===//
334 /// \brief Return true if this instruction could possibly read memory.
335 /// Instructions with this flag set are not necessarily simple load
336 /// instructions, they may load a value and modify it, for example.
337 bool mayLoad() const { return Flags & (1 << MCID::MayLoad); }
339 /// \brief Return true if this instruction could possibly modify memory.
340 /// Instructions with this flag set are not necessarily simple store
341 /// instructions, they may store a modified value based on their operands, or
342 /// may not actually modify anything, for example.
343 bool mayStore() const { return Flags & (1 << MCID::MayStore); }
345 /// \brief Return true if this instruction has side
346 /// effects that are not modeled by other flags. This does not return true
347 /// for instructions whose effects are captured by:
349 /// 1. Their operand list and implicit definition/use list. Register use/def
350 /// info is explicit for instructions.
351 /// 2. Memory accesses. Use mayLoad/mayStore.
352 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
354 /// Examples of side effects would be modifying 'invisible' machine state like
355 /// a control register, flushing a cache, modifying a register invisible to
357 bool hasUnmodeledSideEffects() const {
358 return Flags & (1 << MCID::UnmodeledSideEffects);
361 //===--------------------------------------------------------------------===//
362 // Flags that indicate whether an instruction can be modified by a method.
363 //===--------------------------------------------------------------------===//
365 /// \brief Return true if this may be a 2- or 3-address instruction (of the
366 /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
367 /// exchanged. If this flag is set, then the
368 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
371 /// Note that this flag may be set on instructions that are only commutable
372 /// sometimes. In these cases, the call to commuteInstruction will fail.
373 /// Also note that some instructions require non-trivial modification to
375 bool isCommutable() const { return Flags & (1 << MCID::Commutable); }
377 /// \brief Return true if this is a 2-address instruction which can be changed
378 /// into a 3-address instruction if needed. Doing this transformation can be
379 /// profitable in the register allocator, because it means that the
380 /// instruction can use a 2-address form if possible, but degrade into a less
381 /// efficient form if the source and dest register cannot be assigned to the
382 /// same register. For example, this allows the x86 backend to turn a "shl
383 /// reg, 3" instruction into an LEA instruction, which is the same speed as
384 /// the shift but has bigger code size.
386 /// If this returns true, then the target must implement the
387 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
388 /// is allowed to fail if the transformation isn't valid for this specific
389 /// instruction (e.g. shl reg, 4 on x86).
391 bool isConvertibleTo3Addr() const {
392 return Flags & (1 << MCID::ConvertibleTo3Addr);
395 /// \brief Return true if this instruction requires custom insertion support
396 /// when the DAG scheduler is inserting it into a machine basic block. If
397 /// this is true for the instruction, it basically means that it is a pseudo
398 /// instruction used at SelectionDAG time that is expanded out into magic code
399 /// by the target when MachineInstrs are formed.
401 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
402 /// is used to insert this into the MachineBasicBlock.
403 bool usesCustomInsertionHook() const {
404 return Flags & (1 << MCID::UsesCustomInserter);
407 /// \brief Return true if this instruction requires *adjustment* after
408 /// instruction selection by calling a target hook. For example, this can be
409 /// used to fill in ARM 's' optional operand depending on whether the
410 /// conditional flag register is used.
411 bool hasPostISelHook() const { return Flags & (1 << MCID::HasPostISelHook); }
413 /// \brief Returns true if this instruction is a candidate for remat. This
414 /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
416 /// If this flag is set, the isReallyTriviallyReMaterializable()
417 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
418 /// the instruction is really rematable.
419 bool isRematerializable() const {
420 return Flags & (1 << MCID::Rematerializable);
423 /// \brief Returns true if this instruction has the same cost (or less) than a
424 /// move instruction. This is useful during certain types of optimizations
425 /// (e.g., remat during two-address conversion or machine licm) where we would
426 /// like to remat or hoist the instruction, but not if it costs more than
427 /// moving the instruction into the appropriate register. Note, we are not
428 /// marking copies from and to the same register class with this flag.
430 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
431 /// for different subtargets.
432 bool isAsCheapAsAMove() const { return Flags & (1 << MCID::CheapAsAMove); }
434 /// \brief Returns true if this instruction source operands have special
435 /// register allocation requirements that are not captured by the operand
436 /// register classes. e.g. ARM::STRD's two source registers must be an even /
437 /// odd pair, ARM::STM registers have to be in ascending order. Post-register
438 /// allocation passes should not attempt to change allocations for sources of
439 /// instructions with this flag.
440 bool hasExtraSrcRegAllocReq() const {
441 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
444 /// \brief Returns true if this instruction def operands have special register
445 /// allocation requirements that are not captured by the operand register
446 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
447 /// ARM::LDM registers have to be in ascending order. Post-register
448 /// allocation passes should not attempt to change allocations for definitions
449 /// of instructions with this flag.
450 bool hasExtraDefRegAllocReq() const {
451 return Flags & (1 << MCID::ExtraDefRegAllocReq);
454 /// \brief Return a list of registers that are potentially read by any
455 /// instance of this machine instruction. For example, on X86, the "adc"
456 /// instruction adds two register operands and adds the carry bit in from the
457 /// flags register. In this case, the instruction is marked as implicitly
458 /// reading the flags. Likewise, the variable shift instruction on X86 is
459 /// marked as implicitly reading the 'CL' register, which it always does.
461 /// This method returns null if the instruction has no implicit uses.
462 const uint16_t *getImplicitUses() const { return ImplicitUses; }
464 /// \brief Return the number of implicit uses this instruction has.
465 unsigned getNumImplicitUses() const {
469 for (; ImplicitUses[i]; ++i) /*empty*/
474 /// \brief Return a list of registers that are potentially written by any
475 /// instance of this machine instruction. For example, on X86, many
476 /// instructions implicitly set the flags register. In this case, they are
477 /// marked as setting the FLAGS. Likewise, many instructions always deposit
478 /// their result in a physical register. For example, the X86 divide
479 /// instruction always deposits the quotient and remainder in the EAX/EDX
480 /// registers. For that instruction, this will return a list containing the
481 /// EAX/EDX/EFLAGS registers.
483 /// This method returns null if the instruction has no implicit defs.
484 const uint16_t *getImplicitDefs() const { return ImplicitDefs; }
486 /// \brief Return the number of implicit defs this instruct has.
487 unsigned getNumImplicitDefs() const {
491 for (; ImplicitDefs[i]; ++i) /*empty*/
496 /// \brief Return true if this instruction implicitly
497 /// uses the specified physical register.
498 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
499 if (const uint16_t *ImpUses = ImplicitUses)
500 for (; *ImpUses; ++ImpUses)
506 /// \brief Return true if this instruction implicitly
507 /// defines the specified physical register.
508 bool hasImplicitDefOfPhysReg(unsigned Reg,
509 const MCRegisterInfo *MRI = nullptr) const;
511 /// \brief Return the scheduling class for this instruction. The
512 /// scheduling class is an index into the InstrItineraryData table. This
513 /// returns zero if there is no known scheduling information for the
515 unsigned getSchedClass() const { return SchedClass; }
517 /// \brief Return the number of bytes in the encoding of this instruction,
518 /// or zero if the encoding size cannot be known from the opcode.
519 unsigned getSize() const { return Size; }
521 /// \brief Find the index of the first operand in the
522 /// operand list that is used to represent the predicate. It returns -1 if
524 int findFirstPredOperandIdx() const {
525 if (isPredicable()) {
526 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
527 if (OpInfo[i].isPredicate())
535 /// \brief Return true if this instruction defines the specified physical
536 /// register, either explicitly or implicitly.
537 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
538 const MCRegisterInfo &RI) const;
541 } // end namespace llvm