1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/Support/DataTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Machine Operand Flags and Description
26 //===----------------------------------------------------------------------===//
29 // Operand constraints
30 enum OperandConstraint {
31 TIED_TO = 0, // Must be allocated the same register as.
32 EARLY_CLOBBER // Operand is an early clobber register operand
35 /// OperandFlags - These are flags set on operands, but should be considered
36 /// private, all access should go through the MCOperandInfo accessors.
37 /// See the accessors for a description of what these are.
39 LookupPtrRegClass = 0,
44 /// Operand Type - Operands are tagged with one of the values of this enum.
54 /// MCOperandInfo - This holds information about one operand of a machine
55 /// instruction, indicating the register class for register operands, etc.
59 /// RegClass - This specifies the register class enumeration of the operand
60 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
61 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
62 /// get a dynamic register class.
65 /// Flags - These are flags from the MCOI::OperandFlags enum.
68 /// OperandType - Information about the type of the operand.
71 /// Lower 16 bits are used to specify which constraints are set. The higher 16
72 /// bits are used to specify the value of constraints (4 bits each).
74 /// Currently no other information.
76 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
77 /// requires a callback to look up its register class.
78 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
80 /// isPredicate - Set if this is one of the operands that made up of
81 /// the predicate operand that controls an isPredicable() instruction.
82 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
84 /// isOptionalDef - Set if this operand is a optional def.
86 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
90 //===----------------------------------------------------------------------===//
91 // Machine Instruction Flags and Description
92 //===----------------------------------------------------------------------===//
94 /// MCInstrDesc flags - These should be considered private to the
95 /// implementation of the MCInstrDesc class. Clients should use the predicate
96 /// methods on MCInstrDesc, not use these directly. These all correspond to
97 /// bitfields in the MCInstrDesc::Flags field.
119 UnmodeledSideEffects,
131 /// MCInstrDesc - Describe properties that are true of each instruction in the
132 /// target description file. This captures information about side effects,
133 /// register use and many other things. There is one instance of this struct
134 /// for each target instruction class, and the MachineInstr class points to
135 /// this struct directly to describe itself.
138 unsigned short Opcode; // The opcode number
139 unsigned short NumOperands; // Num of args (may be more if variable_ops)
140 unsigned short NumDefs; // Num of args that are definitions
141 unsigned short SchedClass; // enum identifying instr sched class
142 unsigned short Size; // Number of bytes in encoding.
143 unsigned Flags; // Flags identifying machine instr class
144 uint64_t TSFlags; // Target Specific Flag values
145 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
146 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
147 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
149 /// \brief Returns the value of the specific constraint if
150 /// it is set. Returns -1 if it is not set.
151 int getOperandConstraint(unsigned OpNum,
152 MCOI::OperandConstraint Constraint) const {
153 if (OpNum < NumOperands &&
154 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
155 unsigned Pos = 16 + Constraint * 4;
156 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
161 /// \brief Return the opcode number for this descriptor.
162 unsigned getOpcode() const {
166 /// \brief Return the number of declared MachineOperands for this
167 /// MachineInstruction. Note that variadic (isVariadic() returns true)
168 /// instructions may have additional operands at the end of the list, and note
169 /// that the machine instruction may include implicit register def/uses as
171 unsigned getNumOperands() const {
175 /// \brief Return the number of MachineOperands that are register
176 /// definitions. Register definitions always occur at the start of the
177 /// machine operand list. This is the number of "outs" in the .td file,
178 /// and does not include implicit defs.
179 unsigned getNumDefs() const {
183 /// \brief Return flags of this instruction.
184 unsigned getFlags() const { return Flags; }
186 /// \brief Return true if this instruction can have a variable number of
187 /// operands. In this case, the variable operands will be after the normal
188 /// operands but before the implicit definitions and uses (if any are
190 bool isVariadic() const {
191 return Flags & (1 << MCID::Variadic);
194 /// \brief Set if this instruction has an optional definition, e.g.
195 /// ARM instructions which can set condition code if 's' bit is set.
196 bool hasOptionalDef() const {
197 return Flags & (1 << MCID::HasOptionalDef);
200 /// \brief Return true if this is a pseudo instruction that doesn't
201 /// correspond to a real machine instruction.
203 bool isPseudo() const {
204 return Flags & (1 << MCID::Pseudo);
207 /// \brief Return true if the instruction is a return.
208 bool isReturn() const {
209 return Flags & (1 << MCID::Return);
212 /// \brief Return true if the instruction is a call.
213 bool isCall() const {
214 return Flags & (1 << MCID::Call);
217 /// \brief Returns true if the specified instruction stops control flow
218 /// from executing the instruction immediately following it. Examples include
219 /// unconditional branches and return instructions.
220 bool isBarrier() const {
221 return Flags & (1 << MCID::Barrier);
224 /// \brief Returns true if this instruction part of the terminator for
225 /// a basic block. Typically this is things like return and branch
228 /// Various passes use this to insert code into the bottom of a basic block,
229 /// but before control flow occurs.
230 bool isTerminator() const {
231 return Flags & (1 << MCID::Terminator);
234 /// \brief Returns true if this is a conditional, unconditional, or
235 /// indirect branch. Predicates below can be used to discriminate between
236 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
237 /// get more information.
238 bool isBranch() const {
239 return Flags & (1 << MCID::Branch);
242 /// \brief Return true if this is an indirect branch, such as a
243 /// branch through a register.
244 bool isIndirectBranch() const {
245 return Flags & (1 << MCID::IndirectBranch);
248 /// \brief Return true if this is a branch which may fall
249 /// through to the next instruction or may transfer control flow to some other
250 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
251 /// information about this branch.
252 bool isConditionalBranch() const {
253 return isBranch() & !isBarrier() & !isIndirectBranch();
256 /// \brief Return true if this is a branch which always
257 /// transfers control flow to some other block. The
258 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
259 /// about this branch.
260 bool isUnconditionalBranch() const {
261 return isBranch() & isBarrier() & !isIndirectBranch();
264 /// \brief Return true if this is a branch or an instruction which directly
265 /// writes to the program counter. Considered 'may' affect rather than
266 /// 'does' affect as things like predication are not taken into account.
267 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
268 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
270 unsigned PC = RI.getProgramCounter();
273 if (hasDefOfPhysReg(MI, PC, RI))
275 // A variadic instruction may define PC in the variable operand list.
276 // There's currently no indication of which entries in a variable
277 // list are defs and which are uses. While that's the case, this function
278 // needs to assume they're defs in order to be conservatively correct.
279 for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
280 if (MI.getOperand(i).isReg() &&
281 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
287 /// \brief Return true if this instruction has a predicate operand
288 /// that controls execution. It may be set to 'always', or may be set to other
289 /// values. There are various methods in TargetInstrInfo that can be used to
290 /// control and modify the predicate in this instruction.
291 bool isPredicable() const {
292 return Flags & (1 << MCID::Predicable);
295 /// \brief Return true if this instruction is a comparison.
296 bool isCompare() const {
297 return Flags & (1 << MCID::Compare);
300 /// \brief Return true if this instruction is a move immediate
301 /// (including conditional moves) instruction.
302 bool isMoveImmediate() const {
303 return Flags & (1 << MCID::MoveImm);
306 /// \brief Return true if this instruction is a bitcast instruction.
307 bool isBitcast() const {
308 return Flags & (1 << MCID::Bitcast);
311 /// \brief Return true if this is a select instruction.
312 bool isSelect() const {
313 return Flags & (1 << MCID::Select);
316 /// \brief Return true if this instruction cannot be safely
317 /// duplicated. For example, if the instruction has a unique labels attached
318 /// to it, duplicating it would cause multiple definition errors.
319 bool isNotDuplicable() const {
320 return Flags & (1 << MCID::NotDuplicable);
323 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
324 /// which must be filled by the code generator.
325 bool hasDelaySlot() const {
326 return Flags & (1 << MCID::DelaySlot);
329 /// canFoldAsLoad - Return true for instructions that can be folded as
330 /// memory operands in other instructions. The most common use for this
331 /// is instructions that are simple loads from memory that don't modify
332 /// the loaded value in any way, but it can also be used for instructions
333 /// that can be expressed as constant-pool loads, such as V_SETALLONES
334 /// on x86, to allow them to be folded when it is beneficial.
335 /// This should only be set on instructions that return a value in their
336 /// only virtual register definition.
337 bool canFoldAsLoad() const {
338 return Flags & (1 << MCID::FoldableAsLoad);
341 //===--------------------------------------------------------------------===//
342 // Side Effect Analysis
343 //===--------------------------------------------------------------------===//
345 /// \brief Return true if this instruction could possibly read memory.
346 /// Instructions with this flag set are not necessarily simple load
347 /// instructions, they may load a value and modify it, for example.
348 bool mayLoad() const {
349 return Flags & (1 << MCID::MayLoad);
353 /// \brief Return true if this instruction could possibly modify memory.
354 /// Instructions with this flag set are not necessarily simple store
355 /// instructions, they may store a modified value based on their operands, or
356 /// may not actually modify anything, for example.
357 bool mayStore() const {
358 return Flags & (1 << MCID::MayStore);
361 /// hasUnmodeledSideEffects - Return true if this instruction has side
362 /// effects that are not modeled by other flags. This does not return true
363 /// for instructions whose effects are captured by:
365 /// 1. Their operand list and implicit definition/use list. Register use/def
366 /// info is explicit for instructions.
367 /// 2. Memory accesses. Use mayLoad/mayStore.
368 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
370 /// Examples of side effects would be modifying 'invisible' machine state like
371 /// a control register, flushing a cache, modifying a register invisible to
374 bool hasUnmodeledSideEffects() const {
375 return Flags & (1 << MCID::UnmodeledSideEffects);
378 //===--------------------------------------------------------------------===//
379 // Flags that indicate whether an instruction can be modified by a method.
380 //===--------------------------------------------------------------------===//
382 /// isCommutable - Return true if this may be a 2- or 3-address
383 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
384 /// result if Y and Z are exchanged. If this flag is set, then the
385 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
388 /// Note that this flag may be set on instructions that are only commutable
389 /// sometimes. In these cases, the call to commuteInstruction will fail.
390 /// Also note that some instructions require non-trivial modification to
392 bool isCommutable() const {
393 return Flags & (1 << MCID::Commutable);
396 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
397 /// which can be changed into a 3-address instruction if needed. Doing this
398 /// transformation can be profitable in the register allocator, because it
399 /// means that the instruction can use a 2-address form if possible, but
400 /// degrade into a less efficient form if the source and dest register cannot
401 /// be assigned to the same register. For example, this allows the x86
402 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
403 /// is the same speed as the shift but has bigger code size.
405 /// If this returns true, then the target must implement the
406 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
407 /// is allowed to fail if the transformation isn't valid for this specific
408 /// instruction (e.g. shl reg, 4 on x86).
410 bool isConvertibleTo3Addr() const {
411 return Flags & (1 << MCID::ConvertibleTo3Addr);
414 /// usesCustomInsertionHook - Return true if this instruction requires
415 /// custom insertion support when the DAG scheduler is inserting it into a
416 /// machine basic block. If this is true for the instruction, it basically
417 /// means that it is a pseudo instruction used at SelectionDAG time that is
418 /// expanded out into magic code by the target when MachineInstrs are formed.
420 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
421 /// is used to insert this into the MachineBasicBlock.
422 bool usesCustomInsertionHook() const {
423 return Flags & (1 << MCID::UsesCustomInserter);
426 /// hasPostISelHook - Return true if this instruction requires *adjustment*
427 /// after instruction selection by calling a target hook. For example, this
428 /// can be used to fill in ARM 's' optional operand depending on whether
429 /// the conditional flag register is used.
430 bool hasPostISelHook() const {
431 return Flags & (1 << MCID::HasPostISelHook);
434 /// isRematerializable - Returns true if this instruction is a candidate for
435 /// remat. This flag is deprecated, please don't use it anymore. If this
436 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
437 /// verify the instruction is really rematable.
438 bool isRematerializable() const {
439 return Flags & (1 << MCID::Rematerializable);
442 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
443 /// less) than a move instruction. This is useful during certain types of
444 /// optimizations (e.g., remat during two-address conversion or machine licm)
445 /// where we would like to remat or hoist the instruction, but not if it costs
446 /// more than moving the instruction into the appropriate register. Note, we
447 /// are not marking copies from and to the same register class with this flag.
448 bool isAsCheapAsAMove() const {
449 return Flags & (1 << MCID::CheapAsAMove);
452 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
453 /// have special register allocation requirements that are not captured by the
454 /// operand register classes. e.g. ARM::STRD's two source registers must be an
455 /// even / odd pair, ARM::STM registers have to be in ascending order.
456 /// Post-register allocation passes should not attempt to change allocations
457 /// for sources of instructions with this flag.
458 bool hasExtraSrcRegAllocReq() const {
459 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
462 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
463 /// have special register allocation requirements that are not captured by the
464 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
465 /// even / odd pair, ARM::LDM registers have to be in ascending order.
466 /// Post-register allocation passes should not attempt to change allocations
467 /// for definitions of instructions with this flag.
468 bool hasExtraDefRegAllocReq() const {
469 return Flags & (1 << MCID::ExtraDefRegAllocReq);
473 /// getImplicitUses - Return a list of registers that are potentially
474 /// read by any instance of this machine instruction. For example, on X86,
475 /// the "adc" instruction adds two register operands and adds the carry bit in
476 /// from the flags register. In this case, the instruction is marked as
477 /// implicitly reading the flags. Likewise, the variable shift instruction on
478 /// X86 is marked as implicitly reading the 'CL' register, which it always
481 /// This method returns null if the instruction has no implicit uses.
482 const uint16_t *getImplicitUses() const {
486 /// \brief Return the number of implicit uses this instruction has.
487 unsigned getNumImplicitUses() const {
488 if (ImplicitUses == 0) return 0;
490 for (; ImplicitUses[i]; ++i) /*empty*/;
494 /// getImplicitDefs - Return a list of registers that are potentially
495 /// written by any instance of this machine instruction. For example, on X86,
496 /// many instructions implicitly set the flags register. In this case, they
497 /// are marked as setting the FLAGS. Likewise, many instructions always
498 /// deposit their result in a physical register. For example, the X86 divide
499 /// instruction always deposits the quotient and remainder in the EAX/EDX
500 /// registers. For that instruction, this will return a list containing the
501 /// EAX/EDX/EFLAGS registers.
503 /// This method returns null if the instruction has no implicit defs.
504 const uint16_t *getImplicitDefs() const {
508 /// \brief Return the number of implicit defs this instruct has.
509 unsigned getNumImplicitDefs() const {
510 if (ImplicitDefs == 0) return 0;
512 for (; ImplicitDefs[i]; ++i) /*empty*/;
516 /// \brief Return true if this instruction implicitly
517 /// uses the specified physical register.
518 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
519 if (const uint16_t *ImpUses = ImplicitUses)
520 for (; *ImpUses; ++ImpUses)
521 if (*ImpUses == Reg) return true;
525 /// \brief Return true if this instruction implicitly
526 /// defines the specified physical register.
527 bool hasImplicitDefOfPhysReg(unsigned Reg,
528 const MCRegisterInfo *MRI = 0) const {
529 if (const uint16_t *ImpDefs = ImplicitDefs)
530 for (; *ImpDefs; ++ImpDefs)
531 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
536 /// \brief Return true if this instruction defines the specified physical
537 /// register, either explicitly or implicitly.
538 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
539 const MCRegisterInfo &RI) const {
540 for (int i = 0, e = NumDefs; i != e; ++i)
541 if (MI.getOperand(i).isReg() &&
542 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
544 return hasImplicitDefOfPhysReg(Reg, &RI);
547 /// \brief Return the scheduling class for this instruction. The
548 /// scheduling class is an index into the InstrItineraryData table. This
549 /// returns zero if there is no known scheduling information for the
551 unsigned getSchedClass() const {
555 /// \brief Return the number of bytes in the encoding of this instruction,
556 /// or zero if the encoding size cannot be known from the opcode.
557 unsigned getSize() const {
561 /// \brief Find the index of the first operand in the
562 /// operand list that is used to represent the predicate. It returns -1 if
564 int findFirstPredOperandIdx() const {
565 if (isPredicable()) {
566 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
567 if (OpInfo[i].isPredicate())
574 } // end namespace llvm