1 //===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/Support/DataTypes.h"
22 //===----------------------------------------------------------------------===//
23 // Machine Operand Flags and Description
24 //===----------------------------------------------------------------------===//
27 // Operand constraints
28 enum OperandConstraint {
29 TIED_TO = 0, // Must be allocated the same register as.
30 EARLY_CLOBBER // Operand is an early clobber register operand
33 /// OperandFlags - These are flags set on operands, but should be considered
34 /// private, all access should go through the MCOperandInfo accessors.
35 /// See the accessors for a description of what these are.
37 LookupPtrRegClass = 0,
42 /// Operand Type - Operands are tagged with one of the values of this enum.
52 /// MCOperandInfo - This holds information about one operand of a machine
53 /// instruction, indicating the register class for register operands, etc.
57 /// RegClass - This specifies the register class enumeration of the operand
58 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
59 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60 /// get a dynamic register class.
63 /// Flags - These are flags from the MCOI::OperandFlags enum.
66 /// Lower 16 bits are used to specify which constraints are set. The higher 16
67 /// bits are used to specify the value of constraints (4 bits each).
70 /// OperandType - Information about the type of the operand.
71 MCOI::OperandType OperandType;
72 /// Currently no other information.
74 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75 /// requires a callback to look up its register class.
76 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
78 /// isPredicate - Set if this is one of the operands that made up of
79 /// the predicate operand that controls an isPredicable() instruction.
80 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
82 /// isOptionalDef - Set if this operand is a optional def.
84 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
88 //===----------------------------------------------------------------------===//
89 // Machine Instruction Flags and Description
90 //===----------------------------------------------------------------------===//
92 /// MCInstrDesc flags - These should be considered private to the
93 /// implementation of the MCInstrDesc class. Clients should use the predicate
94 /// methods on MCInstrDesc, not use these directly. These all correspond to
95 /// bitfields in the MCInstrDesc::Flags field.
116 UnmodeledSideEffects,
128 /// MCInstrDesc - Describe properties that are true of each instruction in the
129 /// target description file. This captures information about side effects,
130 /// register use and many other things. There is one instance of this struct
131 /// for each target instruction class, and the MachineInstr class points to
132 /// this struct directly to describe itself.
135 unsigned short Opcode; // The opcode number
136 unsigned short NumOperands; // Num of args (may be more if variable_ops)
137 unsigned short NumDefs; // Num of args that are definitions
138 unsigned short SchedClass; // enum identifying instr sched class
139 unsigned short Size; // Number of bytes in encoding.
140 const char * Name; // Name of the instruction record in td file
141 unsigned Flags; // Flags identifying machine instr class
142 uint64_t TSFlags; // Target Specific Flag values
143 const unsigned *ImplicitUses; // Registers implicitly read by this instr
144 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
145 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
147 /// getOperandConstraint - Returns the value of the specific constraint if
148 /// it is set. Returns -1 if it is not set.
149 int getOperandConstraint(unsigned OpNum,
150 MCOI::OperandConstraint Constraint) const {
151 if (OpNum < NumOperands &&
152 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
153 unsigned Pos = 16 + Constraint * 4;
154 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
159 /// getOpcode - Return the opcode number for this descriptor.
160 unsigned getOpcode() const {
164 /// getName - Return the name of the record in the .td file for this
165 /// instruction, for example "ADD8ri".
166 const char *getName() const {
170 /// getNumOperands - Return the number of declared MachineOperands for this
171 /// MachineInstruction. Note that variadic (isVariadic() returns true)
172 /// instructions may have additional operands at the end of the list, and note
173 /// that the machine instruction may include implicit register def/uses as
175 unsigned getNumOperands() const {
179 /// getNumDefs - Return the number of MachineOperands that are register
180 /// definitions. Register definitions always occur at the start of the
181 /// machine operand list. This is the number of "outs" in the .td file,
182 /// and does not include implicit defs.
183 unsigned getNumDefs() const {
187 /// getFlags - Return flags of this instruction.
189 unsigned short getFlags() const { return Flags; }
191 /// isVariadic - Return true if this instruction can have a variable number of
192 /// operands. In this case, the variable operands will be after the normal
193 /// operands but before the implicit definitions and uses (if any are
195 bool isVariadic() const {
196 return Flags & (1 << MCID::Variadic);
199 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
200 /// ARM instructions which can set condition code if 's' bit is set.
201 bool hasOptionalDef() const {
202 return Flags & (1 << MCID::HasOptionalDef);
205 /// getImplicitUses - Return a list of registers that are potentially
206 /// read by any instance of this machine instruction. For example, on X86,
207 /// the "adc" instruction adds two register operands and adds the carry bit in
208 /// from the flags register. In this case, the instruction is marked as
209 /// implicitly reading the flags. Likewise, the variable shift instruction on
210 /// X86 is marked as implicitly reading the 'CL' register, which it always
213 /// This method returns null if the instruction has no implicit uses.
214 const unsigned *getImplicitUses() const {
218 /// getNumImplicitUses - Return the number of implicit uses this instruction
220 unsigned getNumImplicitUses() const {
221 if (ImplicitUses == 0) return 0;
223 for (; ImplicitUses[i]; ++i) /*empty*/;
227 /// getImplicitDefs - Return a list of registers that are potentially
228 /// written by any instance of this machine instruction. For example, on X86,
229 /// many instructions implicitly set the flags register. In this case, they
230 /// are marked as setting the FLAGS. Likewise, many instructions always
231 /// deposit their result in a physical register. For example, the X86 divide
232 /// instruction always deposits the quotient and remainder in the EAX/EDX
233 /// registers. For that instruction, this will return a list containing the
234 /// EAX/EDX/EFLAGS registers.
236 /// This method returns null if the instruction has no implicit defs.
237 const unsigned *getImplicitDefs() const {
241 /// getNumImplicitDefs - Return the number of implicit defs this instruction
243 unsigned getNumImplicitDefs() const {
244 if (ImplicitDefs == 0) return 0;
246 for (; ImplicitDefs[i]; ++i) /*empty*/;
250 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
251 /// uses the specified physical register.
252 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
253 if (const unsigned *ImpUses = ImplicitUses)
254 for (; *ImpUses; ++ImpUses)
255 if (*ImpUses == Reg) return true;
259 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
260 /// defines the specified physical register.
261 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
262 if (const unsigned *ImpDefs = ImplicitDefs)
263 for (; *ImpDefs; ++ImpDefs)
264 if (*ImpDefs == Reg) return true;
268 /// getSchedClass - Return the scheduling class for this instruction. The
269 /// scheduling class is an index into the InstrItineraryData table. This
270 /// returns zero if there is no known scheduling information for the
273 unsigned getSchedClass() const {
277 /// getSize - Return the number of bytes in the encoding of this instruction,
278 /// or zero if the encoding size cannot be known from the opcode.
279 unsigned getSize() const {
283 /// isPseudo - Return true if this is a pseudo instruction that doesn't
284 /// correspond to a real machine instruction.
286 bool isPseudo() const {
287 return Flags & (1 << MCID::Pseudo);
290 bool isReturn() const {
291 return Flags & (1 << MCID::Return);
294 bool isCall() const {
295 return Flags & (1 << MCID::Call);
298 /// isBarrier - Returns true if the specified instruction stops control flow
299 /// from executing the instruction immediately following it. Examples include
300 /// unconditional branches and return instructions.
301 bool isBarrier() const {
302 return Flags & (1 << MCID::Barrier);
305 /// findFirstPredOperandIdx() - Find the index of the first operand in the
306 /// operand list that is used to represent the predicate. It returns -1 if
308 int findFirstPredOperandIdx() const {
309 if (isPredicable()) {
310 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
311 if (OpInfo[i].isPredicate())
317 /// isTerminator - Returns true if this instruction part of the terminator for
318 /// a basic block. Typically this is things like return and branch
321 /// Various passes use this to insert code into the bottom of a basic block,
322 /// but before control flow occurs.
323 bool isTerminator() const {
324 return Flags & (1 << MCID::Terminator);
327 /// isBranch - Returns true if this is a conditional, unconditional, or
328 /// indirect branch. Predicates below can be used to discriminate between
329 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
330 /// get more information.
331 bool isBranch() const {
332 return Flags & (1 << MCID::Branch);
335 /// isIndirectBranch - Return true if this is an indirect branch, such as a
336 /// branch through a register.
337 bool isIndirectBranch() const {
338 return Flags & (1 << MCID::IndirectBranch);
341 /// isConditionalBranch - Return true if this is a branch which may fall
342 /// through to the next instruction or may transfer control flow to some other
343 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
344 /// information about this branch.
345 bool isConditionalBranch() const {
346 return isBranch() & !isBarrier() & !isIndirectBranch();
349 /// isUnconditionalBranch - Return true if this is a branch which always
350 /// transfers control flow to some other block. The
351 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
352 /// about this branch.
353 bool isUnconditionalBranch() const {
354 return isBranch() & isBarrier() & !isIndirectBranch();
357 // isPredicable - Return true if this instruction has a predicate operand that
358 // controls execution. It may be set to 'always', or may be set to other
359 /// values. There are various methods in TargetInstrInfo that can be used to
360 /// control and modify the predicate in this instruction.
361 bool isPredicable() const {
362 return Flags & (1 << MCID::Predicable);
365 /// isCompare - Return true if this instruction is a comparison.
366 bool isCompare() const {
367 return Flags & (1 << MCID::Compare);
370 /// isMoveImmediate - Return true if this instruction is a move immediate
371 /// (including conditional moves) instruction.
372 bool isMoveImmediate() const {
373 return Flags & (1 << MCID::MoveImm);
376 /// isBitcast - Return true if this instruction is a bitcast instruction.
378 bool isBitcast() const {
379 return Flags & (1 << MCID::Bitcast);
382 /// isNotDuplicable - Return true if this instruction cannot be safely
383 /// duplicated. For example, if the instruction has a unique labels attached
384 /// to it, duplicating it would cause multiple definition errors.
385 bool isNotDuplicable() const {
386 return Flags & (1 << MCID::NotDuplicable);
389 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
390 /// which must be filled by the code generator.
391 bool hasDelaySlot() const {
392 return Flags & (1 << MCID::DelaySlot);
395 /// canFoldAsLoad - Return true for instructions that can be folded as
396 /// memory operands in other instructions. The most common use for this
397 /// is instructions that are simple loads from memory that don't modify
398 /// the loaded value in any way, but it can also be used for instructions
399 /// that can be expressed as constant-pool loads, such as V_SETALLONES
400 /// on x86, to allow them to be folded when it is beneficial.
401 /// This should only be set on instructions that return a value in their
402 /// only virtual register definition.
403 bool canFoldAsLoad() const {
404 return Flags & (1 << MCID::FoldableAsLoad);
407 //===--------------------------------------------------------------------===//
408 // Side Effect Analysis
409 //===--------------------------------------------------------------------===//
411 /// mayLoad - Return true if this instruction could possibly read memory.
412 /// Instructions with this flag set are not necessarily simple load
413 /// instructions, they may load a value and modify it, for example.
414 bool mayLoad() const {
415 return Flags & (1 << MCID::MayLoad);
419 /// mayStore - Return true if this instruction could possibly modify memory.
420 /// Instructions with this flag set are not necessarily simple store
421 /// instructions, they may store a modified value based on their operands, or
422 /// may not actually modify anything, for example.
423 bool mayStore() const {
424 return Flags & (1 << MCID::MayStore);
427 /// hasUnmodeledSideEffects - Return true if this instruction has side
428 /// effects that are not modeled by other flags. This does not return true
429 /// for instructions whose effects are captured by:
431 /// 1. Their operand list and implicit definition/use list. Register use/def
432 /// info is explicit for instructions.
433 /// 2. Memory accesses. Use mayLoad/mayStore.
434 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
436 /// Examples of side effects would be modifying 'invisible' machine state like
437 /// a control register, flushing a cache, modifying a register invisible to
440 bool hasUnmodeledSideEffects() const {
441 return Flags & (1 << MCID::UnmodeledSideEffects);
444 //===--------------------------------------------------------------------===//
445 // Flags that indicate whether an instruction can be modified by a method.
446 //===--------------------------------------------------------------------===//
448 /// isCommutable - Return true if this may be a 2- or 3-address
449 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
450 /// result if Y and Z are exchanged. If this flag is set, then the
451 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
454 /// Note that this flag may be set on instructions that are only commutable
455 /// sometimes. In these cases, the call to commuteInstruction will fail.
456 /// Also note that some instructions require non-trivial modification to
458 bool isCommutable() const {
459 return Flags & (1 << MCID::Commutable);
462 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
463 /// which can be changed into a 3-address instruction if needed. Doing this
464 /// transformation can be profitable in the register allocator, because it
465 /// means that the instruction can use a 2-address form if possible, but
466 /// degrade into a less efficient form if the source and dest register cannot
467 /// be assigned to the same register. For example, this allows the x86
468 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
469 /// is the same speed as the shift but has bigger code size.
471 /// If this returns true, then the target must implement the
472 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
473 /// is allowed to fail if the transformation isn't valid for this specific
474 /// instruction (e.g. shl reg, 4 on x86).
476 bool isConvertibleTo3Addr() const {
477 return Flags & (1 << MCID::ConvertibleTo3Addr);
480 /// usesCustomInsertionHook - Return true if this instruction requires
481 /// custom insertion support when the DAG scheduler is inserting it into a
482 /// machine basic block. If this is true for the instruction, it basically
483 /// means that it is a pseudo instruction used at SelectionDAG time that is
484 /// expanded out into magic code by the target when MachineInstrs are formed.
486 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
487 /// is used to insert this into the MachineBasicBlock.
488 bool usesCustomInsertionHook() const {
489 return Flags & (1 << MCID::UsesCustomInserter);
492 /// hasPostISelHook - Return true if this instruction requires *adjustment*
493 /// after instruction selection by calling a target hook. For example, this
494 /// can be used to fill in ARM 's' optional operand depending on whether
495 /// the conditional flag register is used.
496 bool hasPostISelHook() const {
497 return Flags & (1 << MCID::HasPostISelHook);
500 /// isRematerializable - Returns true if this instruction is a candidate for
501 /// remat. This flag is deprecated, please don't use it anymore. If this
502 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
503 /// verify the instruction is really rematable.
504 bool isRematerializable() const {
505 return Flags & (1 << MCID::Rematerializable);
508 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
509 /// less) than a move instruction. This is useful during certain types of
510 /// optimizations (e.g., remat during two-address conversion or machine licm)
511 /// where we would like to remat or hoist the instruction, but not if it costs
512 /// more than moving the instruction into the appropriate register. Note, we
513 /// are not marking copies from and to the same register class with this flag.
514 bool isAsCheapAsAMove() const {
515 return Flags & (1 << MCID::CheapAsAMove);
518 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
519 /// have special register allocation requirements that are not captured by the
520 /// operand register classes. e.g. ARM::STRD's two source registers must be an
521 /// even / odd pair, ARM::STM registers have to be in ascending order.
522 /// Post-register allocation passes should not attempt to change allocations
523 /// for sources of instructions with this flag.
524 bool hasExtraSrcRegAllocReq() const {
525 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
528 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
529 /// have special register allocation requirements that are not captured by the
530 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
531 /// even / odd pair, ARM::LDM registers have to be in ascending order.
532 /// Post-register allocation passes should not attempt to change allocations
533 /// for definitions of instructions with this flag.
534 bool hasExtraDefRegAllocReq() const {
535 return Flags & (1 << MCID::ExtraDefRegAllocReq);
539 } // end namespace llvm