1 //===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/Support/DataTypes.h"
22 //===----------------------------------------------------------------------===//
23 // Machine Operand Flags and Description
24 //===----------------------------------------------------------------------===//
27 // Operand constraints
28 enum OperandConstraint {
29 TIED_TO = 0, // Must be allocated the same register as.
30 EARLY_CLOBBER // Operand is an early clobber register operand
33 /// OperandFlags - These are flags set on operands, but should be considered
34 /// private, all access should go through the MCOperandInfo accessors.
35 /// See the accessors for a description of what these are.
37 LookupPtrRegClass = 0,
42 /// Operand Type - Operands are tagged with one of the values of this enum.
52 /// MCOperandInfo - This holds information about one operand of a machine
53 /// instruction, indicating the register class for register operands, etc.
57 /// RegClass - This specifies the register class enumeration of the operand
58 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
59 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60 /// get a dynamic register class.
63 /// Flags - These are flags from the MCOI::OperandFlags enum.
66 /// Lower 16 bits are used to specify which constraints are set. The higher 16
67 /// bits are used to specify the value of constraints (4 bits each).
70 /// OperandType - Information about the type of the operand.
71 MCOI::OperandType OperandType;
72 /// Currently no other information.
74 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75 /// requires a callback to look up its register class.
76 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
78 /// isPredicate - Set if this is one of the operands that made up of
79 /// the predicate operand that controls an isPredicable() instruction.
80 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
82 /// isOptionalDef - Set if this operand is a optional def.
84 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
88 //===----------------------------------------------------------------------===//
89 // Machine Instruction Flags and Description
90 //===----------------------------------------------------------------------===//
92 /// MCInstrDesc flags - These should be considered private to the
93 /// implementation of the MCInstrDesc class. Clients should use the predicate
94 /// methods on MCInstrDesc, not use these directly. These all correspond to
95 /// bitfields in the MCInstrDesc::Flags field.
115 UnmodeledSideEffects,
127 /// MCInstrDesc - Describe properties that are true of each instruction in the
128 /// target description file. This captures information about side effects,
129 /// register use and many other things. There is one instance of this struct
130 /// for each target instruction class, and the MachineInstr class points to
131 /// this struct directly to describe itself.
134 unsigned short Opcode; // The opcode number
135 unsigned short NumOperands; // Num of args (may be more if variable_ops)
136 unsigned short NumDefs; // Num of args that are definitions
137 unsigned short SchedClass; // enum identifying instr sched class
138 unsigned short Size; // Number of bytes in encoding.
139 const char * Name; // Name of the instruction record in td file
140 unsigned Flags; // Flags identifying machine instr class
141 uint64_t TSFlags; // Target Specific Flag values
142 const unsigned *ImplicitUses; // Registers implicitly read by this instr
143 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
144 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
146 /// getOperandConstraint - Returns the value of the specific constraint if
147 /// it is set. Returns -1 if it is not set.
148 int getOperandConstraint(unsigned OpNum,
149 MCOI::OperandConstraint Constraint) const {
150 if (OpNum < NumOperands &&
151 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
152 unsigned Pos = 16 + Constraint * 4;
153 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
158 /// getOpcode - Return the opcode number for this descriptor.
159 unsigned getOpcode() const {
163 /// getName - Return the name of the record in the .td file for this
164 /// instruction, for example "ADD8ri".
165 const char *getName() const {
169 /// getNumOperands - Return the number of declared MachineOperands for this
170 /// MachineInstruction. Note that variadic (isVariadic() returns true)
171 /// instructions may have additional operands at the end of the list, and note
172 /// that the machine instruction may include implicit register def/uses as
174 unsigned getNumOperands() const {
178 /// getNumDefs - Return the number of MachineOperands that are register
179 /// definitions. Register definitions always occur at the start of the
180 /// machine operand list. This is the number of "outs" in the .td file,
181 /// and does not include implicit defs.
182 unsigned getNumDefs() const {
186 /// isVariadic - Return true if this instruction can have a variable number of
187 /// operands. In this case, the variable operands will be after the normal
188 /// operands but before the implicit definitions and uses (if any are
190 bool isVariadic() const {
191 return Flags & (1 << MCID::Variadic);
194 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
195 /// ARM instructions which can set condition code if 's' bit is set.
196 bool hasOptionalDef() const {
197 return Flags & (1 << MCID::HasOptionalDef);
200 /// getImplicitUses - Return a list of registers that are potentially
201 /// read by any instance of this machine instruction. For example, on X86,
202 /// the "adc" instruction adds two register operands and adds the carry bit in
203 /// from the flags register. In this case, the instruction is marked as
204 /// implicitly reading the flags. Likewise, the variable shift instruction on
205 /// X86 is marked as implicitly reading the 'CL' register, which it always
208 /// This method returns null if the instruction has no implicit uses.
209 const unsigned *getImplicitUses() const {
213 /// getNumImplicitUses - Return the number of implicit uses this instruction
215 unsigned getNumImplicitUses() const {
216 if (ImplicitUses == 0) return 0;
218 for (; ImplicitUses[i]; ++i) /*empty*/;
222 /// getImplicitDefs - Return a list of registers that are potentially
223 /// written by any instance of this machine instruction. For example, on X86,
224 /// many instructions implicitly set the flags register. In this case, they
225 /// are marked as setting the FLAGS. Likewise, many instructions always
226 /// deposit their result in a physical register. For example, the X86 divide
227 /// instruction always deposits the quotient and remainder in the EAX/EDX
228 /// registers. For that instruction, this will return a list containing the
229 /// EAX/EDX/EFLAGS registers.
231 /// This method returns null if the instruction has no implicit defs.
232 const unsigned *getImplicitDefs() const {
236 /// getNumImplicitDefs - Return the number of implicit defs this instruction
238 unsigned getNumImplicitDefs() const {
239 if (ImplicitDefs == 0) return 0;
241 for (; ImplicitDefs[i]; ++i) /*empty*/;
245 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
246 /// uses the specified physical register.
247 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
248 if (const unsigned *ImpUses = ImplicitUses)
249 for (; *ImpUses; ++ImpUses)
250 if (*ImpUses == Reg) return true;
254 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
255 /// defines the specified physical register.
256 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
257 if (const unsigned *ImpDefs = ImplicitDefs)
258 for (; *ImpDefs; ++ImpDefs)
259 if (*ImpDefs == Reg) return true;
263 /// getSchedClass - Return the scheduling class for this instruction. The
264 /// scheduling class is an index into the InstrItineraryData table. This
265 /// returns zero if there is no known scheduling information for the
268 unsigned getSchedClass() const {
272 /// getSize - Return the number of bytes in the encoding of this instruction,
273 /// or zero if the encoding size cannot be known from the opcode.
274 unsigned getSize() const {
278 bool isReturn() const {
279 return Flags & (1 << MCID::Return);
282 bool isCall() const {
283 return Flags & (1 << MCID::Call);
286 /// isBarrier - Returns true if the specified instruction stops control flow
287 /// from executing the instruction immediately following it. Examples include
288 /// unconditional branches and return instructions.
289 bool isBarrier() const {
290 return Flags & (1 << MCID::Barrier);
293 /// findFirstPredOperandIdx() - Find the index of the first operand in the
294 /// operand list that is used to represent the predicate. It returns -1 if
296 int findFirstPredOperandIdx() const {
297 if (isPredicable()) {
298 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
299 if (OpInfo[i].isPredicate())
305 /// isTerminator - Returns true if this instruction part of the terminator for
306 /// a basic block. Typically this is things like return and branch
309 /// Various passes use this to insert code into the bottom of a basic block,
310 /// but before control flow occurs.
311 bool isTerminator() const {
312 return Flags & (1 << MCID::Terminator);
315 /// isBranch - Returns true if this is a conditional, unconditional, or
316 /// indirect branch. Predicates below can be used to discriminate between
317 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
318 /// get more information.
319 bool isBranch() const {
320 return Flags & (1 << MCID::Branch);
323 /// isIndirectBranch - Return true if this is an indirect branch, such as a
324 /// branch through a register.
325 bool isIndirectBranch() const {
326 return Flags & (1 << MCID::IndirectBranch);
329 /// isConditionalBranch - Return true if this is a branch which may fall
330 /// through to the next instruction or may transfer control flow to some other
331 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
332 /// information about this branch.
333 bool isConditionalBranch() const {
334 return isBranch() & !isBarrier() & !isIndirectBranch();
337 /// isUnconditionalBranch - Return true if this is a branch which always
338 /// transfers control flow to some other block. The
339 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
340 /// about this branch.
341 bool isUnconditionalBranch() const {
342 return isBranch() & isBarrier() & !isIndirectBranch();
345 // isPredicable - Return true if this instruction has a predicate operand that
346 // controls execution. It may be set to 'always', or may be set to other
347 /// values. There are various methods in TargetInstrInfo that can be used to
348 /// control and modify the predicate in this instruction.
349 bool isPredicable() const {
350 return Flags & (1 << MCID::Predicable);
353 /// isCompare - Return true if this instruction is a comparison.
354 bool isCompare() const {
355 return Flags & (1 << MCID::Compare);
358 /// isMoveImmediate - Return true if this instruction is a move immediate
359 /// (including conditional moves) instruction.
360 bool isMoveImmediate() const {
361 return Flags & (1 << MCID::MoveImm);
364 /// isBitcast - Return true if this instruction is a bitcast instruction.
366 bool isBitcast() const {
367 return Flags & (1 << MCID::Bitcast);
370 /// isNotDuplicable - Return true if this instruction cannot be safely
371 /// duplicated. For example, if the instruction has a unique labels attached
372 /// to it, duplicating it would cause multiple definition errors.
373 bool isNotDuplicable() const {
374 return Flags & (1 << MCID::NotDuplicable);
377 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
378 /// which must be filled by the code generator.
379 bool hasDelaySlot() const {
380 return Flags & (1 << MCID::DelaySlot);
383 /// canFoldAsLoad - Return true for instructions that can be folded as
384 /// memory operands in other instructions. The most common use for this
385 /// is instructions that are simple loads from memory that don't modify
386 /// the loaded value in any way, but it can also be used for instructions
387 /// that can be expressed as constant-pool loads, such as V_SETALLONES
388 /// on x86, to allow them to be folded when it is beneficial.
389 /// This should only be set on instructions that return a value in their
390 /// only virtual register definition.
391 bool canFoldAsLoad() const {
392 return Flags & (1 << MCID::FoldableAsLoad);
395 //===--------------------------------------------------------------------===//
396 // Side Effect Analysis
397 //===--------------------------------------------------------------------===//
399 /// mayLoad - Return true if this instruction could possibly read memory.
400 /// Instructions with this flag set are not necessarily simple load
401 /// instructions, they may load a value and modify it, for example.
402 bool mayLoad() const {
403 return Flags & (1 << MCID::MayLoad);
407 /// mayStore - Return true if this instruction could possibly modify memory.
408 /// Instructions with this flag set are not necessarily simple store
409 /// instructions, they may store a modified value based on their operands, or
410 /// may not actually modify anything, for example.
411 bool mayStore() const {
412 return Flags & (1 << MCID::MayStore);
415 /// hasUnmodeledSideEffects - Return true if this instruction has side
416 /// effects that are not modeled by other flags. This does not return true
417 /// for instructions whose effects are captured by:
419 /// 1. Their operand list and implicit definition/use list. Register use/def
420 /// info is explicit for instructions.
421 /// 2. Memory accesses. Use mayLoad/mayStore.
422 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
424 /// Examples of side effects would be modifying 'invisible' machine state like
425 /// a control register, flushing a cache, modifying a register invisible to
428 bool hasUnmodeledSideEffects() const {
429 return Flags & (1 << MCID::UnmodeledSideEffects);
432 //===--------------------------------------------------------------------===//
433 // Flags that indicate whether an instruction can be modified by a method.
434 //===--------------------------------------------------------------------===//
436 /// isCommutable - Return true if this may be a 2- or 3-address
437 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
438 /// result if Y and Z are exchanged. If this flag is set, then the
439 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
442 /// Note that this flag may be set on instructions that are only commutable
443 /// sometimes. In these cases, the call to commuteInstruction will fail.
444 /// Also note that some instructions require non-trivial modification to
446 bool isCommutable() const {
447 return Flags & (1 << MCID::Commutable);
450 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
451 /// which can be changed into a 3-address instruction if needed. Doing this
452 /// transformation can be profitable in the register allocator, because it
453 /// means that the instruction can use a 2-address form if possible, but
454 /// degrade into a less efficient form if the source and dest register cannot
455 /// be assigned to the same register. For example, this allows the x86
456 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
457 /// is the same speed as the shift but has bigger code size.
459 /// If this returns true, then the target must implement the
460 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
461 /// is allowed to fail if the transformation isn't valid for this specific
462 /// instruction (e.g. shl reg, 4 on x86).
464 bool isConvertibleTo3Addr() const {
465 return Flags & (1 << MCID::ConvertibleTo3Addr);
468 /// usesCustomInsertionHook - Return true if this instruction requires
469 /// custom insertion support when the DAG scheduler is inserting it into a
470 /// machine basic block. If this is true for the instruction, it basically
471 /// means that it is a pseudo instruction used at SelectionDAG time that is
472 /// expanded out into magic code by the target when MachineInstrs are formed.
474 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
475 /// is used to insert this into the MachineBasicBlock.
476 bool usesCustomInsertionHook() const {
477 return Flags & (1 << MCID::UsesCustomInserter);
480 /// hasPostISelHook - Return true if this instruction requires *adjustment*
481 /// after instruction selection by calling a target hook. For example, this
482 /// can be used to fill in ARM 's' optional operand depending on whether
483 /// the conditional flag register is used.
484 bool hasPostISelHook() const {
485 return Flags & (1 << MCID::HasPostISelHook);
488 /// isRematerializable - Returns true if this instruction is a candidate for
489 /// remat. This flag is deprecated, please don't use it anymore. If this
490 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
491 /// verify the instruction is really rematable.
492 bool isRematerializable() const {
493 return Flags & (1 << MCID::Rematerializable);
496 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
497 /// less) than a move instruction. This is useful during certain types of
498 /// optimizations (e.g., remat during two-address conversion or machine licm)
499 /// where we would like to remat or hoist the instruction, but not if it costs
500 /// more than moving the instruction into the appropriate register. Note, we
501 /// are not marking copies from and to the same register class with this flag.
502 bool isAsCheapAsAMove() const {
503 return Flags & (1 << MCID::CheapAsAMove);
506 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
507 /// have special register allocation requirements that are not captured by the
508 /// operand register classes. e.g. ARM::STRD's two source registers must be an
509 /// even / odd pair, ARM::STM registers have to be in ascending order.
510 /// Post-register allocation passes should not attempt to change allocations
511 /// for sources of instructions with this flag.
512 bool hasExtraSrcRegAllocReq() const {
513 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
516 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
517 /// have special register allocation requirements that are not captured by the
518 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
519 /// even / odd pair, ARM::LDM registers have to be in ascending order.
520 /// Post-register allocation passes should not attempt to change allocations
521 /// for definitions of instructions with this flag.
522 bool hasExtraDefRegAllocReq() const {
523 return Flags & (1 << MCID::ExtraDefRegAllocReq);
527 } // end namespace llvm