1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/DataTypes.h"
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
30 // Operand constraints
31 enum OperandConstraint {
32 TIED_TO = 0, // Must be allocated the same register as.
33 EARLY_CLOBBER // Operand is an early clobber register operand
36 /// OperandFlags - These are flags set on operands, but should be considered
37 /// private, all access should go through the MCOperandInfo accessors.
38 /// See the accessors for a description of what these are.
40 LookupPtrRegClass = 0,
45 /// Operand Type - Operands are tagged with one of the values of this enum.
55 /// MCOperandInfo - This holds information about one operand of a machine
56 /// instruction, indicating the register class for register operands, etc.
60 /// RegClass - This specifies the register class enumeration of the operand
61 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
62 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
63 /// get a dynamic register class.
66 /// Flags - These are flags from the MCOI::OperandFlags enum.
69 /// OperandType - Information about the type of the operand.
72 /// Lower 16 bits are used to specify which constraints are set. The higher 16
73 /// bits are used to specify the value of constraints (4 bits each).
75 /// Currently no other information.
77 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
78 /// requires a callback to look up its register class.
79 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
81 /// isPredicate - Set if this is one of the operands that made up of
82 /// the predicate operand that controls an isPredicable() instruction.
83 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
85 /// isOptionalDef - Set if this operand is a optional def.
87 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
91 //===----------------------------------------------------------------------===//
92 // Machine Instruction Flags and Description
93 //===----------------------------------------------------------------------===//
95 /// MCInstrDesc flags - These should be considered private to the
96 /// implementation of the MCInstrDesc class. Clients should use the predicate
97 /// methods on MCInstrDesc, not use these directly. These all correspond to
98 /// bitfields in the MCInstrDesc::Flags field.
120 UnmodeledSideEffects,
132 /// MCInstrDesc - Describe properties that are true of each instruction in the
133 /// target description file. This captures information about side effects,
134 /// register use and many other things. There is one instance of this struct
135 /// for each target instruction class, and the MachineInstr class points to
136 /// this struct directly to describe itself.
139 unsigned short Opcode; // The opcode number
140 unsigned short NumOperands; // Num of args (may be more if variable_ops)
141 unsigned short NumDefs; // Num of args that are definitions
142 unsigned short SchedClass; // enum identifying instr sched class
143 unsigned short Size; // Number of bytes in encoding.
144 unsigned Flags; // Flags identifying machine instr class
145 uint64_t TSFlags; // Target Specific Flag values
146 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
147 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
148 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
149 uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
150 // A complex method to determine is a certain is deprecated or not, and return
151 // the reason for deprecation.
152 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
154 /// \brief Returns the value of the specific constraint if
155 /// it is set. Returns -1 if it is not set.
156 int getOperandConstraint(unsigned OpNum,
157 MCOI::OperandConstraint Constraint) const {
158 if (OpNum < NumOperands &&
159 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
160 unsigned Pos = 16 + Constraint * 4;
161 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
166 /// \brief Returns true if a certain instruction is deprecated and if so
167 /// returns the reason in \p Info.
168 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
169 std::string &Info) const {
170 if (ComplexDeprecationInfo)
171 return ComplexDeprecationInfo(MI, STI, Info);
172 if (DeprecatedFeatureMask != 0) {
173 // FIXME: it would be nice to include the subtarget feature here.
180 /// \brief Return the opcode number for this descriptor.
181 unsigned getOpcode() const {
185 /// \brief Return the number of declared MachineOperands for this
186 /// MachineInstruction. Note that variadic (isVariadic() returns true)
187 /// instructions may have additional operands at the end of the list, and note
188 /// that the machine instruction may include implicit register def/uses as
190 unsigned getNumOperands() const {
194 /// \brief Return the number of MachineOperands that are register
195 /// definitions. Register definitions always occur at the start of the
196 /// machine operand list. This is the number of "outs" in the .td file,
197 /// and does not include implicit defs.
198 unsigned getNumDefs() const {
202 /// \brief Return flags of this instruction.
203 unsigned getFlags() const { return Flags; }
205 /// \brief Return true if this instruction can have a variable number of
206 /// operands. In this case, the variable operands will be after the normal
207 /// operands but before the implicit definitions and uses (if any are
209 bool isVariadic() const {
210 return Flags & (1 << MCID::Variadic);
213 /// \brief Set if this instruction has an optional definition, e.g.
214 /// ARM instructions which can set condition code if 's' bit is set.
215 bool hasOptionalDef() const {
216 return Flags & (1 << MCID::HasOptionalDef);
219 /// \brief Return true if this is a pseudo instruction that doesn't
220 /// correspond to a real machine instruction.
222 bool isPseudo() const {
223 return Flags & (1 << MCID::Pseudo);
226 /// \brief Return true if the instruction is a return.
227 bool isReturn() const {
228 return Flags & (1 << MCID::Return);
231 /// \brief Return true if the instruction is a call.
232 bool isCall() const {
233 return Flags & (1 << MCID::Call);
236 /// \brief Returns true if the specified instruction stops control flow
237 /// from executing the instruction immediately following it. Examples include
238 /// unconditional branches and return instructions.
239 bool isBarrier() const {
240 return Flags & (1 << MCID::Barrier);
243 /// \brief Returns true if this instruction part of the terminator for
244 /// a basic block. Typically this is things like return and branch
247 /// Various passes use this to insert code into the bottom of a basic block,
248 /// but before control flow occurs.
249 bool isTerminator() const {
250 return Flags & (1 << MCID::Terminator);
253 /// \brief Returns true if this is a conditional, unconditional, or
254 /// indirect branch. Predicates below can be used to discriminate between
255 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
256 /// get more information.
257 bool isBranch() const {
258 return Flags & (1 << MCID::Branch);
261 /// \brief Return true if this is an indirect branch, such as a
262 /// branch through a register.
263 bool isIndirectBranch() const {
264 return Flags & (1 << MCID::IndirectBranch);
267 /// \brief Return true if this is a branch which may fall
268 /// through to the next instruction or may transfer control flow to some other
269 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
270 /// information about this branch.
271 bool isConditionalBranch() const {
272 return isBranch() & !isBarrier() & !isIndirectBranch();
275 /// \brief Return true if this is a branch which always
276 /// transfers control flow to some other block. The
277 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
278 /// about this branch.
279 bool isUnconditionalBranch() const {
280 return isBranch() & isBarrier() & !isIndirectBranch();
283 /// \brief Return true if this is a branch or an instruction which directly
284 /// writes to the program counter. Considered 'may' affect rather than
285 /// 'does' affect as things like predication are not taken into account.
286 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
287 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
289 unsigned PC = RI.getProgramCounter();
292 if (hasDefOfPhysReg(MI, PC, RI))
294 // A variadic instruction may define PC in the variable operand list.
295 // There's currently no indication of which entries in a variable
296 // list are defs and which are uses. While that's the case, this function
297 // needs to assume they're defs in order to be conservatively correct.
298 for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
299 if (MI.getOperand(i).isReg() &&
300 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
306 /// \brief Return true if this instruction has a predicate operand
307 /// that controls execution. It may be set to 'always', or may be set to other
308 /// values. There are various methods in TargetInstrInfo that can be used to
309 /// control and modify the predicate in this instruction.
310 bool isPredicable() const {
311 return Flags & (1 << MCID::Predicable);
314 /// \brief Return true if this instruction is a comparison.
315 bool isCompare() const {
316 return Flags & (1 << MCID::Compare);
319 /// \brief Return true if this instruction is a move immediate
320 /// (including conditional moves) instruction.
321 bool isMoveImmediate() const {
322 return Flags & (1 << MCID::MoveImm);
325 /// \brief Return true if this instruction is a bitcast instruction.
326 bool isBitcast() const {
327 return Flags & (1 << MCID::Bitcast);
330 /// \brief Return true if this is a select instruction.
331 bool isSelect() const {
332 return Flags & (1 << MCID::Select);
335 /// \brief Return true if this instruction cannot be safely
336 /// duplicated. For example, if the instruction has a unique labels attached
337 /// to it, duplicating it would cause multiple definition errors.
338 bool isNotDuplicable() const {
339 return Flags & (1 << MCID::NotDuplicable);
342 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
343 /// which must be filled by the code generator.
344 bool hasDelaySlot() const {
345 return Flags & (1 << MCID::DelaySlot);
348 /// canFoldAsLoad - Return true for instructions that can be folded as
349 /// memory operands in other instructions. The most common use for this
350 /// is instructions that are simple loads from memory that don't modify
351 /// the loaded value in any way, but it can also be used for instructions
352 /// that can be expressed as constant-pool loads, such as V_SETALLONES
353 /// on x86, to allow them to be folded when it is beneficial.
354 /// This should only be set on instructions that return a value in their
355 /// only virtual register definition.
356 bool canFoldAsLoad() const {
357 return Flags & (1 << MCID::FoldableAsLoad);
360 //===--------------------------------------------------------------------===//
361 // Side Effect Analysis
362 //===--------------------------------------------------------------------===//
364 /// \brief Return true if this instruction could possibly read memory.
365 /// Instructions with this flag set are not necessarily simple load
366 /// instructions, they may load a value and modify it, for example.
367 bool mayLoad() const {
368 return Flags & (1 << MCID::MayLoad);
372 /// \brief Return true if this instruction could possibly modify memory.
373 /// Instructions with this flag set are not necessarily simple store
374 /// instructions, they may store a modified value based on their operands, or
375 /// may not actually modify anything, for example.
376 bool mayStore() const {
377 return Flags & (1 << MCID::MayStore);
380 /// hasUnmodeledSideEffects - Return true if this instruction has side
381 /// effects that are not modeled by other flags. This does not return true
382 /// for instructions whose effects are captured by:
384 /// 1. Their operand list and implicit definition/use list. Register use/def
385 /// info is explicit for instructions.
386 /// 2. Memory accesses. Use mayLoad/mayStore.
387 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
389 /// Examples of side effects would be modifying 'invisible' machine state like
390 /// a control register, flushing a cache, modifying a register invisible to
393 bool hasUnmodeledSideEffects() const {
394 return Flags & (1 << MCID::UnmodeledSideEffects);
397 //===--------------------------------------------------------------------===//
398 // Flags that indicate whether an instruction can be modified by a method.
399 //===--------------------------------------------------------------------===//
401 /// isCommutable - Return true if this may be a 2- or 3-address
402 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
403 /// result if Y and Z are exchanged. If this flag is set, then the
404 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
407 /// Note that this flag may be set on instructions that are only commutable
408 /// sometimes. In these cases, the call to commuteInstruction will fail.
409 /// Also note that some instructions require non-trivial modification to
411 bool isCommutable() const {
412 return Flags & (1 << MCID::Commutable);
415 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
416 /// which can be changed into a 3-address instruction if needed. Doing this
417 /// transformation can be profitable in the register allocator, because it
418 /// means that the instruction can use a 2-address form if possible, but
419 /// degrade into a less efficient form if the source and dest register cannot
420 /// be assigned to the same register. For example, this allows the x86
421 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
422 /// is the same speed as the shift but has bigger code size.
424 /// If this returns true, then the target must implement the
425 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
426 /// is allowed to fail if the transformation isn't valid for this specific
427 /// instruction (e.g. shl reg, 4 on x86).
429 bool isConvertibleTo3Addr() const {
430 return Flags & (1 << MCID::ConvertibleTo3Addr);
433 /// usesCustomInsertionHook - Return true if this instruction requires
434 /// custom insertion support when the DAG scheduler is inserting it into a
435 /// machine basic block. If this is true for the instruction, it basically
436 /// means that it is a pseudo instruction used at SelectionDAG time that is
437 /// expanded out into magic code by the target when MachineInstrs are formed.
439 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
440 /// is used to insert this into the MachineBasicBlock.
441 bool usesCustomInsertionHook() const {
442 return Flags & (1 << MCID::UsesCustomInserter);
445 /// hasPostISelHook - Return true if this instruction requires *adjustment*
446 /// after instruction selection by calling a target hook. For example, this
447 /// can be used to fill in ARM 's' optional operand depending on whether
448 /// the conditional flag register is used.
449 bool hasPostISelHook() const {
450 return Flags & (1 << MCID::HasPostISelHook);
453 /// isRematerializable - Returns true if this instruction is a candidate for
454 /// remat. This flag is deprecated, please don't use it anymore. If this
455 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
456 /// verify the instruction is really rematable.
457 bool isRematerializable() const {
458 return Flags & (1 << MCID::Rematerializable);
461 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
462 /// less) than a move instruction. This is useful during certain types of
463 /// optimizations (e.g., remat during two-address conversion or machine licm)
464 /// where we would like to remat or hoist the instruction, but not if it costs
465 /// more than moving the instruction into the appropriate register. Note, we
466 /// are not marking copies from and to the same register class with this flag.
467 bool isAsCheapAsAMove() const {
468 return Flags & (1 << MCID::CheapAsAMove);
471 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
472 /// have special register allocation requirements that are not captured by the
473 /// operand register classes. e.g. ARM::STRD's two source registers must be an
474 /// even / odd pair, ARM::STM registers have to be in ascending order.
475 /// Post-register allocation passes should not attempt to change allocations
476 /// for sources of instructions with this flag.
477 bool hasExtraSrcRegAllocReq() const {
478 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
481 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
482 /// have special register allocation requirements that are not captured by the
483 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
484 /// even / odd pair, ARM::LDM registers have to be in ascending order.
485 /// Post-register allocation passes should not attempt to change allocations
486 /// for definitions of instructions with this flag.
487 bool hasExtraDefRegAllocReq() const {
488 return Flags & (1 << MCID::ExtraDefRegAllocReq);
492 /// getImplicitUses - Return a list of registers that are potentially
493 /// read by any instance of this machine instruction. For example, on X86,
494 /// the "adc" instruction adds two register operands and adds the carry bit in
495 /// from the flags register. In this case, the instruction is marked as
496 /// implicitly reading the flags. Likewise, the variable shift instruction on
497 /// X86 is marked as implicitly reading the 'CL' register, which it always
500 /// This method returns null if the instruction has no implicit uses.
501 const uint16_t *getImplicitUses() const {
505 /// \brief Return the number of implicit uses this instruction has.
506 unsigned getNumImplicitUses() const {
507 if (ImplicitUses == 0) return 0;
509 for (; ImplicitUses[i]; ++i) /*empty*/;
513 /// getImplicitDefs - Return a list of registers that are potentially
514 /// written by any instance of this machine instruction. For example, on X86,
515 /// many instructions implicitly set the flags register. In this case, they
516 /// are marked as setting the FLAGS. Likewise, many instructions always
517 /// deposit their result in a physical register. For example, the X86 divide
518 /// instruction always deposits the quotient and remainder in the EAX/EDX
519 /// registers. For that instruction, this will return a list containing the
520 /// EAX/EDX/EFLAGS registers.
522 /// This method returns null if the instruction has no implicit defs.
523 const uint16_t *getImplicitDefs() const {
527 /// \brief Return the number of implicit defs this instruct has.
528 unsigned getNumImplicitDefs() const {
529 if (ImplicitDefs == 0) return 0;
531 for (; ImplicitDefs[i]; ++i) /*empty*/;
535 /// \brief Return true if this instruction implicitly
536 /// uses the specified physical register.
537 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
538 if (const uint16_t *ImpUses = ImplicitUses)
539 for (; *ImpUses; ++ImpUses)
540 if (*ImpUses == Reg) return true;
544 /// \brief Return true if this instruction implicitly
545 /// defines the specified physical register.
546 bool hasImplicitDefOfPhysReg(unsigned Reg,
547 const MCRegisterInfo *MRI = 0) const {
548 if (const uint16_t *ImpDefs = ImplicitDefs)
549 for (; *ImpDefs; ++ImpDefs)
550 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
555 /// \brief Return true if this instruction defines the specified physical
556 /// register, either explicitly or implicitly.
557 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
558 const MCRegisterInfo &RI) const {
559 for (int i = 0, e = NumDefs; i != e; ++i)
560 if (MI.getOperand(i).isReg() &&
561 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
563 return hasImplicitDefOfPhysReg(Reg, &RI);
566 /// \brief Return the scheduling class for this instruction. The
567 /// scheduling class is an index into the InstrItineraryData table. This
568 /// returns zero if there is no known scheduling information for the
570 unsigned getSchedClass() const {
574 /// \brief Return the number of bytes in the encoding of this instruction,
575 /// or zero if the encoding size cannot be known from the opcode.
576 unsigned getSize() const {
580 /// \brief Find the index of the first operand in the
581 /// operand list that is used to represent the predicate. It returns -1 if
583 int findFirstPredOperandIdx() const {
584 if (isPredicable()) {
585 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
586 if (OpInfo[i].isPredicate())
593 } // end namespace llvm