1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// MCRegisterClass - Base class of TargetRegisterClass.
26 class MCRegisterClass {
28 typedef const unsigned* iterator;
29 typedef const unsigned* const_iterator;
33 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
35 const bool Allocatable;
36 const iterator RegsBegin, RegsEnd;
37 const unsigned char *const RegSet;
38 const unsigned RegSetSize;
40 /// getID() - Return the register class ID number.
42 unsigned getID() const { return ID; }
44 /// getName() - Return the register class name for debugging.
46 const char *getName() const { return Name; }
48 /// begin/end - Return all of the registers in this class.
50 iterator begin() const { return RegsBegin; }
51 iterator end() const { return RegsEnd; }
53 /// getNumRegs - Return the number of registers in this class.
55 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
57 /// getRegister - Return the specified register in the class.
59 unsigned getRegister(unsigned i) const {
60 assert(i < getNumRegs() && "Register number out of range!");
64 /// contains - Return true if the specified register is included in this
65 /// register class. This does not include virtual registers.
66 bool contains(unsigned Reg) const {
67 unsigned InByte = Reg % 8;
68 unsigned Byte = Reg / 8;
69 if (Byte >= RegSetSize)
71 return (RegSet[Byte] & (1 << InByte)) != 0;
74 /// contains - Return true if both registers are in this class.
75 bool contains(unsigned Reg1, unsigned Reg2) const {
76 return contains(Reg1) && contains(Reg2);
79 /// getSize - Return the size of the register in bytes, which is also the size
80 /// of a stack slot allocated to hold a spilled copy of this register.
81 unsigned getSize() const { return RegSize; }
83 /// getAlignment - Return the minimum required alignment for a register of
85 unsigned getAlignment() const { return Alignment; }
87 /// getCopyCost - Return the cost of copying a value between two registers in
88 /// this class. A negative number means the register class is very expensive
89 /// to copy e.g. status flag register classes.
90 int getCopyCost() const { return CopyCost; }
92 /// isAllocatable - Return true if this register class may be used to create
93 /// virtual registers.
94 bool isAllocatable() const { return Allocatable; }
97 /// MCRegisterDesc - This record contains all of the information known about
98 /// a particular register. The Overlaps field contains a pointer to a zero
99 /// terminated array of registers that this register aliases, starting with
100 /// itself. This is needed for architectures like X86 which have AL alias AX
101 /// alias EAX. The SubRegs field is a zero terminated array of registers that
102 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
103 /// AX. The SuperRegs field is a zero terminated array of registers that are
104 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
107 struct MCRegisterDesc {
108 const char *Name; // Printable name for the reg (for debugging)
109 int Overlaps; // Overlapping registers, described above
110 int SubRegs; // Sub-register set, described above
111 int SuperRegs; // Super-register set, described above
114 /// MCRegisterInfo base class - We assume that the target defines a static
115 /// array of MCRegisterDesc objects that represent all of the machine
116 /// registers that the target has. As such, we simply have to track a pointer
117 /// to this array so that we can turn register number into a register
120 /// Note this class is designed to be a base class of TargetRegisterInfo, which
121 /// is the interface used by codegen. However, specific targets *should never*
122 /// specialize this class. MCRegisterInfo should only contain getters to access
123 /// TableGen generated physical register data. It must not be extended with
126 class MCRegisterInfo {
128 typedef const MCRegisterClass *regclass_iterator;
130 const MCRegisterDesc *Desc; // Pointer to the descriptor array
131 unsigned NumRegs; // Number of entries in the array
132 unsigned RAReg; // Return address register
133 const MCRegisterClass *Classes; // Pointer to the regclass array
134 unsigned NumClasses; // Number of entries in the array
135 const unsigned *Overlaps; // Pointer to the overlaps array
136 const unsigned *SubRegs; // Pointer to the subregs array
137 const unsigned *SuperRegs; // Pointer to the superregs array
138 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
139 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
140 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
141 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
142 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
145 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
146 /// auto-generated routines. *DO NOT USE*.
147 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
148 const MCRegisterClass *C, unsigned NC,
149 const unsigned *O, const unsigned *Sub,
150 const unsigned *Super) {
161 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
162 /// register number mapping. Called by TableGen auto-generated routines.
164 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
166 EHL2DwarfRegs[LLVMReg] = DwarfReg;
168 L2DwarfRegs[LLVMReg] = DwarfReg;
171 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
172 /// register number mapping. Called by TableGen auto-generated routines.
174 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
176 EHDwarf2LRegs[DwarfReg] = LLVMReg;
178 Dwarf2LRegs[DwarfReg] = LLVMReg;
181 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
182 /// number mapping. By default the SEH register number is just the same
183 /// as the LLVM register number.
184 /// FIXME: TableGen these numbers. Currently this requires target specific
185 /// initialization code.
186 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
187 L2SEHRegs[LLVMReg] = SEHReg;
190 /// getRARegister - This method should return the register where the return
191 /// address can be found.
192 unsigned getRARegister() const {
196 const MCRegisterDesc &operator[](unsigned RegNo) const {
197 assert(RegNo < NumRegs &&
198 "Attempting to access record for invalid register number!");
202 /// Provide a get method, equivalent to [], but more useful if we have a
203 /// pointer to this object.
205 const MCRegisterDesc &get(unsigned RegNo) const {
206 return operator[](RegNo);
209 /// getAliasSet - Return the set of registers aliased by the specified
210 /// register, or a null list of there are none. The list returned is zero
213 const unsigned *getAliasSet(unsigned RegNo) const {
214 // The Overlaps set always begins with Reg itself.
215 if (get(RegNo).Overlaps < 0) return 0;
216 return Overlaps + get(RegNo).Overlaps + 1;
219 /// getOverlaps - Return a list of registers that overlap Reg, including
220 /// itself. This is the same as the alias set except Reg is included in the
222 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
224 const unsigned *getOverlaps(unsigned RegNo) const {
225 if (get(RegNo).Overlaps < 0) return 0;
226 return Overlaps + get(RegNo).Overlaps;
229 /// getSubRegisters - Return the list of registers that are sub-registers of
230 /// the specified register, or a null list of there are none. The list
231 /// returned is zero terminated and sorted according to super-sub register
232 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
234 const unsigned *getSubRegisters(unsigned RegNo) const {
235 if (get(RegNo).SubRegs < 0) return 0;
236 return SubRegs + get(RegNo).SubRegs;
239 /// getSuperRegisters - Return the list of registers that are super-registers
240 /// of the specified register, or a null list of there are none. The list
241 /// returned is zero terminated and sorted according to super-sub register
242 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
244 const unsigned *getSuperRegisters(unsigned RegNo) const {
245 if (get(RegNo).SuperRegs < 0) return 0;
246 return SuperRegs + get(RegNo).SuperRegs;
249 /// getName - Return the human-readable symbolic target-specific name for the
250 /// specified physical register.
251 const char *getName(unsigned RegNo) const {
252 return get(RegNo).Name;
255 /// getNumRegs - Return the number of registers this target has (useful for
256 /// sizing arrays holding per register information)
257 unsigned getNumRegs() const {
261 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
262 /// number. Returns -1 if there is no equivalent value. The second
263 /// parameter allows targets to use different numberings for EH info and
265 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
266 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
267 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
268 if (I == M.end()) return -1;
272 /// getLLVMRegNum - Map a dwarf register back to a target register.
274 int getLLVMRegNum(unsigned RegNum, bool isEH) const {
275 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
276 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
278 llvm_unreachable("Invalid RegNum");
283 /// getSEHRegNum - Map a target register to an equivalent SEH register
284 /// number. Returns LLVM register number if there is no equivalent value.
285 int getSEHRegNum(unsigned RegNum) const {
286 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
287 if (I == L2SEHRegs.end()) return (int)RegNum;
291 regclass_iterator regclass_begin() const { return Classes; }
292 regclass_iterator regclass_end() const { return Classes+NumClasses; }
294 unsigned getNumRegClasses() const {
295 return (unsigned)(regclass_end()-regclass_begin());
298 /// getRegClass - Returns the register class associated with the enumeration
299 /// value. See class MCOperandInfo.
300 const MCRegisterClass getRegClass(unsigned i) const {
301 assert(i < getNumRegClasses() && "Register Class ID out of range");
306 } // End llvm namespace