1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// MCRegisterClass - Base class of TargetRegisterClass.
26 class MCRegisterClass {
28 typedef const uint16_t* iterator;
29 typedef const uint16_t* const_iterator;
32 const iterator RegsBegin;
33 const uint8_t *const RegSet;
34 const uint16_t RegsSize;
35 const uint16_t RegSetSize;
37 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
38 const int8_t CopyCost;
39 const bool Allocatable;
41 /// getID() - Return the register class ID number.
43 unsigned getID() const { return ID; }
45 /// getName() - Return the register class name for debugging.
47 const char *getName() const { return Name; }
49 /// begin/end - Return all of the registers in this class.
51 iterator begin() const { return RegsBegin; }
52 iterator end() const { return RegsBegin + RegsSize; }
54 /// getNumRegs - Return the number of registers in this class.
56 unsigned getNumRegs() const { return RegsSize; }
58 /// getRegister - Return the specified register in the class.
60 unsigned getRegister(unsigned i) const {
61 assert(i < getNumRegs() && "Register number out of range!");
65 /// contains - Return true if the specified register is included in this
66 /// register class. This does not include virtual registers.
67 bool contains(unsigned Reg) const {
68 unsigned InByte = Reg % 8;
69 unsigned Byte = Reg / 8;
70 if (Byte >= RegSetSize)
72 return (RegSet[Byte] & (1 << InByte)) != 0;
75 /// contains - Return true if both registers are in this class.
76 bool contains(unsigned Reg1, unsigned Reg2) const {
77 return contains(Reg1) && contains(Reg2);
80 /// getSize - Return the size of the register in bytes, which is also the size
81 /// of a stack slot allocated to hold a spilled copy of this register.
82 unsigned getSize() const { return RegSize; }
84 /// getAlignment - Return the minimum required alignment for a register of
86 unsigned getAlignment() const { return Alignment; }
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost; }
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable; }
98 /// MCRegisterDesc - This record contains all of the information known about
99 /// a particular register. The Overlaps field contains a pointer to a zero
100 /// terminated array of registers that this register aliases, starting with
101 /// itself. This is needed for architectures like X86 which have AL alias AX
102 /// alias EAX. The SubRegs field is a zero terminated array of registers that
103 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
104 /// AX. The SuperRegs field is a zero terminated array of registers that are
105 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
108 struct MCRegisterDesc {
109 uint32_t Name; // Printable name for the reg (for debugging)
110 uint32_t Overlaps; // Overlapping registers, described above
111 uint32_t SubRegs; // Sub-register set, described above
112 uint32_t SuperRegs; // Super-register set, described above
114 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
115 // sub-register in SubRegs.
116 uint32_t SubRegIndices;
118 // RegUnits - Points to the list of register units. The low 4 bits holds the
119 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
123 /// MCRegisterInfo base class - We assume that the target defines a static
124 /// array of MCRegisterDesc objects that represent all of the machine
125 /// registers that the target has. As such, we simply have to track a pointer
126 /// to this array so that we can turn register number into a register
129 /// Note this class is designed to be a base class of TargetRegisterInfo, which
130 /// is the interface used by codegen. However, specific targets *should never*
131 /// specialize this class. MCRegisterInfo should only contain getters to access
132 /// TableGen generated physical register data. It must not be extended with
135 class MCRegisterInfo {
137 typedef const MCRegisterClass *regclass_iterator;
139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140 /// performed with a binary search.
141 struct DwarfLLVMRegPair {
145 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
148 const MCRegisterDesc *Desc; // Pointer to the descriptor array
149 unsigned NumRegs; // Number of entries in the array
150 unsigned RAReg; // Return address register
151 const MCRegisterClass *Classes; // Pointer to the regclass array
152 unsigned NumClasses; // Number of entries in the array
153 unsigned NumRegUnits; // Number of regunits.
154 const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
155 const uint16_t *DiffLists; // Pointer to the difflists array
156 const char *RegStrings; // Pointer to the string table.
157 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
159 unsigned NumSubRegIndices; // Number of subreg indices.
160 const uint16_t *RegEncodingTable; // Pointer to array of register
163 unsigned L2DwarfRegsSize;
164 unsigned EHL2DwarfRegsSize;
165 unsigned Dwarf2LRegsSize;
166 unsigned EHDwarf2LRegsSize;
167 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
168 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
169 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
170 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
171 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
174 /// DiffListIterator - Base iterator class that can traverse the
175 /// differentially encoded register and regunit lists in DiffLists.
176 /// Don't use this class directly, use one of the specialized sub-classes
178 class DiffListIterator {
180 const uint16_t *List;
183 /// Create an invalid iterator. Call init() to point to something useful.
184 DiffListIterator() : Val(0), List(0) {}
186 /// init - Point the iterator to InitVal, decoding subsequent values from
187 /// DiffList. The iterator will initially point to InitVal, sub-classes are
188 /// responsible for skipping the seed value if it is not part of the list.
189 void init(uint16_t InitVal, const uint16_t *DiffList) {
194 /// advance - Move to the next list position, return the applied
195 /// differential. This function does not detect the end of the list, that
196 /// is the caller's responsibility (by checking for a 0 return value).
198 assert(isValid() && "Cannot move off the end of the list.");
199 uint16_t D = *List++;
206 /// isValid - returns true if this iterator is not yet at the end.
207 bool isValid() const { return List; }
209 /// Dereference the iterator to get the value at the current position.
210 unsigned operator*() const { return Val; }
212 /// Pre-increment to move to the next position.
214 // The end of the list is encoded as a 0 differential.
220 // These iterators are allowed to sub-class DiffListIterator and access
221 // internal list pointers.
222 friend class MCSubRegIterator;
223 friend class MCSuperRegIterator;
224 friend class MCRegAliasIterator;
225 friend class MCRegUnitIterator;
226 friend class MCRegUnitRootIterator;
228 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
229 /// auto-generated routines. *DO NOT USE*.
230 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
231 const MCRegisterClass *C, unsigned NC,
232 const uint16_t (*RURoots)[2],
236 const uint16_t *SubIndices,
238 const uint16_t *RET) {
244 RegStrings = Strings;
246 RegUnitRoots = RURoots;
248 SubRegIndices = SubIndices;
249 NumSubRegIndices = NumIndices;
250 RegEncodingTable = RET;
253 /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf
254 /// register number mapping. Called by TableGen auto-generated routines.
256 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
260 EHL2DwarfRegsSize = Size;
263 L2DwarfRegsSize = Size;
267 /// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM
268 /// register number mapping. Called by TableGen auto-generated routines.
270 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
274 EHDwarf2LRegsSize = Size;
277 Dwarf2LRegsSize = Size;
281 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
282 /// number mapping. By default the SEH register number is just the same
283 /// as the LLVM register number.
284 /// FIXME: TableGen these numbers. Currently this requires target specific
285 /// initialization code.
286 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
287 L2SEHRegs[LLVMReg] = SEHReg;
290 /// getRARegister - This method should return the register where the return
291 /// address can be found.
292 unsigned getRARegister() const {
296 const MCRegisterDesc &operator[](unsigned RegNo) const {
297 assert(RegNo < NumRegs &&
298 "Attempting to access record for invalid register number!");
302 /// Provide a get method, equivalent to [], but more useful if we have a
303 /// pointer to this object.
305 const MCRegisterDesc &get(unsigned RegNo) const {
306 return operator[](RegNo);
309 /// getSubReg - Returns the physical register number of sub-register "Index"
310 /// for physical register RegNo. Return zero if the sub-register does not
312 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
314 /// getMatchingSuperReg - Return a super-register of the specified register
315 /// Reg so its sub-register of index SubIdx is Reg.
316 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
317 const MCRegisterClass *RC) const;
319 /// getSubRegIndex - For a given register pair, return the sub-register index
320 /// if the second register is a sub-register of the first. Return zero
322 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
324 /// getName - Return the human-readable symbolic target-specific name for the
325 /// specified physical register.
326 const char *getName(unsigned RegNo) const {
327 return RegStrings + get(RegNo).Name;
330 /// getNumRegs - Return the number of registers this target has (useful for
331 /// sizing arrays holding per register information)
332 unsigned getNumRegs() const {
336 /// getNumRegUnits - Return the number of (native) register units in the
337 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
338 /// can be accessed through MCRegUnitIterator defined below.
339 unsigned getNumRegUnits() const {
343 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
344 /// number. Returns -1 if there is no equivalent value. The second
345 /// parameter allows targets to use different numberings for EH info and
347 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
349 /// getLLVMRegNum - Map a dwarf register back to a target register.
351 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
353 /// getSEHRegNum - Map a target register to an equivalent SEH register
354 /// number. Returns LLVM register number if there is no equivalent value.
355 int getSEHRegNum(unsigned RegNum) const;
357 regclass_iterator regclass_begin() const { return Classes; }
358 regclass_iterator regclass_end() const { return Classes+NumClasses; }
360 unsigned getNumRegClasses() const {
361 return (unsigned)(regclass_end()-regclass_begin());
364 /// getRegClass - Returns the register class associated with the enumeration
365 /// value. See class MCOperandInfo.
366 const MCRegisterClass getRegClass(unsigned i) const {
367 assert(i < getNumRegClasses() && "Register Class ID out of range");
371 /// getEncodingValue - Returns the encoding for RegNo
372 uint16_t getEncodingValue(unsigned RegNo) const {
373 assert(RegNo < NumRegs &&
374 "Attempting to get encoding for invalid register number!");
375 return RegEncodingTable[RegNo];
380 //===----------------------------------------------------------------------===//
381 // Register List Iterators
382 //===----------------------------------------------------------------------===//
384 // MCRegisterInfo provides lists of super-registers, sub-registers, and
385 // aliasing registers. Use these iterator classes to traverse the lists.
387 /// MCSubRegIterator enumerates all sub-registers of Reg.
388 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
390 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
391 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
396 /// MCSuperRegIterator enumerates all super-registers of Reg.
397 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
399 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
400 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
405 /// MCRegAliasIterator enumerates all registers aliasing Reg.
406 /// If IncludeSelf is set, Reg itself is included in the list.
407 class MCRegAliasIterator : public MCRegisterInfo::DiffListIterator {
409 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
411 init(Reg, MCRI->DiffLists + MCRI->get(Reg).Overlaps);
412 // Initially, the iterator points to Reg itself.
418 //===----------------------------------------------------------------------===//
420 //===----------------------------------------------------------------------===//
422 // Register units are used to compute register aliasing. Every register has at
423 // least one register unit, but it can have more. Two registers overlap if and
424 // only if they have a common register unit.
426 // A target with a complicated sub-register structure will typically have many
427 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
428 // the number of register units in the target.
430 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
431 // in ascending numerical order.
432 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
434 /// MCRegUnitIterator - Create an iterator that traverses the register units
436 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
437 // Decode the RegUnits MCRegisterDesc field.
438 unsigned RU = MCRI->get(Reg).RegUnits;
439 unsigned Scale = RU & 15;
440 unsigned Offset = RU >> 4;
442 // Initialize the iterator to Reg * Scale, and the List pointer to
443 // DiffLists + Offset.
444 init(Reg * Scale, MCRI->DiffLists + Offset);
446 // That may not be a valid unit, we need to advance by one to get the real
447 // unit number. The first differential can be 0 which would normally
448 // terminate the list, but since we know every register has at least one
449 // unit, we can allow a 0 differential here.
454 // Each register unit has one or two root registers. The complete set of
455 // registers containing a register unit is the union of the roots and their
456 // super-registers. All registers aliasing Unit can be visited like this:
458 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
459 // unsigned Root = *RI;
461 // for (MCSuperRegIterator SI(Root, MCRI); SI.isValid(); ++SI)
465 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
466 class MCRegUnitRootIterator {
470 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
471 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
472 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
473 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
476 /// Dereference to get the current root register.
477 unsigned operator*() const {
481 /// isValid - Check if the iterator is at the end of the list.
482 bool isValid() const {
486 /// Preincrement to move to the next root register.
488 assert(isValid() && "Cannot move off the end of the list.");
494 } // End llvm namespace