1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
24 /// MCRegisterClass - Base class of TargetRegisterClass.
25 class MCRegisterClass {
27 typedef const unsigned* iterator;
28 typedef const unsigned* const_iterator;
32 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
34 const bool Allocatable;
35 const iterator RegsBegin, RegsEnd;
36 const unsigned char *const RegSet;
37 const unsigned RegSetSize;
39 MCRegisterClass(unsigned id, const char *name,
40 unsigned RS, unsigned Al, int CC, bool Allocable,
41 iterator RB, iterator RE, const unsigned char *Bits,
43 : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
44 Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE), RegSet(Bits),
45 RegSetSize(NumBytes) {
46 for (iterator i = RegsBegin; i != RegsEnd; ++i)
47 assert(contains(*i) && "Bit field corrupted.");
50 /// getID() - Return the register class ID number.
52 unsigned getID() const { return ID; }
54 /// getName() - Return the register class name for debugging.
56 const char *getName() const { return Name; }
58 /// begin/end - Return all of the registers in this class.
60 iterator begin() const { return RegsBegin; }
61 iterator end() const { return RegsEnd; }
63 /// getNumRegs - Return the number of registers in this class.
65 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
67 /// getRegister - Return the specified register in the class.
69 unsigned getRegister(unsigned i) const {
70 assert(i < getNumRegs() && "Register number out of range!");
74 /// contains - Return true if the specified register is included in this
75 /// register class. This does not include virtual registers.
76 bool contains(unsigned Reg) const {
77 unsigned InByte = Reg % 8;
78 unsigned Byte = Reg / 8;
79 if (Byte >= RegSetSize)
81 return (RegSet[Byte] & (1 << InByte)) != 0;
84 /// contains - Return true if both registers are in this class.
85 bool contains(unsigned Reg1, unsigned Reg2) const {
86 return contains(Reg1) && contains(Reg2);
89 /// getSize - Return the size of the register in bytes, which is also the size
90 /// of a stack slot allocated to hold a spilled copy of this register.
91 unsigned getSize() const { return RegSize; }
93 /// getAlignment - Return the minimum required alignment for a register of
95 unsigned getAlignment() const { return Alignment; }
97 /// getCopyCost - Return the cost of copying a value between two registers in
98 /// this class. A negative number means the register class is very expensive
99 /// to copy e.g. status flag register classes.
100 int getCopyCost() const { return CopyCost; }
102 /// isAllocatable - Return true if this register class may be used to create
103 /// virtual registers.
104 bool isAllocatable() const { return Allocatable; }
107 /// MCRegisterDesc - This record contains all of the information known about
108 /// a particular register. The Overlaps field contains a pointer to a zero
109 /// terminated array of registers that this register aliases, starting with
110 /// itself. This is needed for architectures like X86 which have AL alias AX
111 /// alias EAX. The SubRegs field is a zero terminated array of registers that
112 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
113 /// AX. The SuperRegs field is a zero terminated array of registers that are
114 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
117 struct MCRegisterDesc {
118 const char *Name; // Printable name for the reg (for debugging)
119 const unsigned *Overlaps; // Overlapping registers, described above
120 const unsigned *SubRegs; // Sub-register set, described above
121 const unsigned *SuperRegs; // Super-register set, described above
124 /// MCRegisterInfo base class - We assume that the target defines a static
125 /// array of MCRegisterDesc objects that represent all of the machine
126 /// registers that the target has. As such, we simply have to track a pointer
127 /// to this array so that we can turn register number into a register
130 /// Note this class is designed to be a base class of TargetRegisterInfo, which
131 /// is the interface used by codegen. However, specific targets *should never*
132 /// specialize this class. MCRegisterInfo should only contain getters to access
133 /// TableGen generated physical register data. It must not be extended with
136 class MCRegisterInfo {
138 typedef const MCRegisterClass *regclass_iterator;
140 const MCRegisterDesc *Desc; // Pointer to the descriptor array
141 unsigned NumRegs; // Number of entries in the array
142 unsigned RAReg; // Return address register
143 const MCRegisterClass *Classes; // Pointer to the regclass array
144 unsigned NumClasses; // Number of entries in the array
145 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
146 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
147 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
148 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
149 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
152 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
153 /// auto-generated routines. *DO NOT USE*.
154 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
155 const MCRegisterClass *C, unsigned NC) {
163 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
164 /// register number mapping. Called by TableGen auto-generated routines.
166 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
168 EHL2DwarfRegs[LLVMReg] = DwarfReg;
170 L2DwarfRegs[LLVMReg] = DwarfReg;
173 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
174 /// register number mapping. Called by TableGen auto-generated routines.
176 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
178 EHDwarf2LRegs[DwarfReg] = LLVMReg;
180 Dwarf2LRegs[DwarfReg] = LLVMReg;
183 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
184 /// number mapping. By default the SEH register number is just the same
185 /// as the LLVM register number.
186 /// FIXME: TableGen these numbers. Currently this requires target specific
187 /// initialization code.
188 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
189 L2SEHRegs[LLVMReg] = SEHReg;
192 /// getRARegister - This method should return the register where the return
193 /// address can be found.
194 unsigned getRARegister() const {
198 const MCRegisterDesc &operator[](unsigned RegNo) const {
199 assert(RegNo < NumRegs &&
200 "Attempting to access record for invalid register number!");
204 /// Provide a get method, equivalent to [], but more useful if we have a
205 /// pointer to this object.
207 const MCRegisterDesc &get(unsigned RegNo) const {
208 return operator[](RegNo);
211 /// getAliasSet - Return the set of registers aliased by the specified
212 /// register, or a null list of there are none. The list returned is zero
215 const unsigned *getAliasSet(unsigned RegNo) const {
216 // The Overlaps set always begins with Reg itself.
217 return get(RegNo).Overlaps + 1;
220 /// getOverlaps - Return a list of registers that overlap Reg, including
221 /// itself. This is the same as the alias set except Reg is included in the
223 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
225 const unsigned *getOverlaps(unsigned RegNo) const {
226 return get(RegNo).Overlaps;
229 /// getSubRegisters - Return the list of registers that are sub-registers of
230 /// the specified register, or a null list of there are none. The list
231 /// returned is zero terminated and sorted according to super-sub register
232 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
234 const unsigned *getSubRegisters(unsigned RegNo) const {
235 return get(RegNo).SubRegs;
238 /// getSuperRegisters - Return the list of registers that are super-registers
239 /// of the specified register, or a null list of there are none. The list
240 /// returned is zero terminated and sorted according to super-sub register
241 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
243 const unsigned *getSuperRegisters(unsigned RegNo) const {
244 return get(RegNo).SuperRegs;
247 /// getName - Return the human-readable symbolic target-specific name for the
248 /// specified physical register.
249 const char *getName(unsigned RegNo) const {
250 return get(RegNo).Name;
253 /// getNumRegs - Return the number of registers this target has (useful for
254 /// sizing arrays holding per register information)
255 unsigned getNumRegs() const {
259 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
260 /// number. Returns -1 if there is no equivalent value. The second
261 /// parameter allows targets to use different numberings for EH info and
263 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
264 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
265 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
266 if (I == M.end()) return -1;
270 /// getLLVMRegNum - Map a dwarf register back to a target register.
272 int getLLVMRegNum(unsigned RegNum, bool isEH) const {
273 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
274 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
276 assert(0 && "Invalid RegNum");
282 /// getSEHRegNum - Map a target register to an equivalent SEH register
283 /// number. Returns LLVM register number if there is no equivalent value.
284 int getSEHRegNum(unsigned RegNum) const {
285 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
286 if (I == L2SEHRegs.end()) return (int)RegNum;
290 regclass_iterator regclass_begin() const { return Classes; }
291 regclass_iterator regclass_end() const { return Classes+NumClasses; }
293 unsigned getNumRegClasses() const {
294 return (unsigned)(regclass_end()-regclass_begin());
297 /// getRegClass - Returns the register class associated with the enumeration
298 /// value. See class MCOperandInfo.
299 const MCRegisterClass getRegClass(unsigned i) const {
300 assert(i < getNumRegClasses() && "Register Class ID out of range");
305 } // End llvm namespace