1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/DenseSet.h"
25 /// MCRegisterClass - Base class of TargetRegisterClass.
26 class MCRegisterClass {
28 typedef const unsigned* iterator;
29 typedef const unsigned* const_iterator;
33 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
35 const bool Allocatable;
36 const iterator RegsBegin, RegsEnd;
37 DenseSet<unsigned> RegSet;
39 MCRegisterClass(unsigned id, const char *name,
40 unsigned RS, unsigned Al, int CC, bool Allocable,
41 iterator RB, iterator RE)
42 : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
43 Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {
44 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
48 /// getID() - Return the register class ID number.
50 unsigned getID() const { return ID; }
52 /// getName() - Return the register class name for debugging.
54 const char *getName() const { return Name; }
56 /// begin/end - Return all of the registers in this class.
58 iterator begin() const { return RegsBegin; }
59 iterator end() const { return RegsEnd; }
61 /// getNumRegs - Return the number of registers in this class.
63 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
65 /// getRegister - Return the specified register in the class.
67 unsigned getRegister(unsigned i) const {
68 assert(i < getNumRegs() && "Register number out of range!");
72 /// contains - Return true if the specified register is included in this
73 /// register class. This does not include virtual registers.
74 bool contains(unsigned Reg) const {
75 return RegSet.count(Reg);
78 /// contains - Return true if both registers are in this class.
79 bool contains(unsigned Reg1, unsigned Reg2) const {
80 return contains(Reg1) && contains(Reg2);
83 /// getSize - Return the size of the register in bytes, which is also the size
84 /// of a stack slot allocated to hold a spilled copy of this register.
85 unsigned getSize() const { return RegSize; }
87 /// getAlignment - Return the minimum required alignment for a register of
89 unsigned getAlignment() const { return Alignment; }
91 /// getCopyCost - Return the cost of copying a value between two registers in
92 /// this class. A negative number means the register class is very expensive
93 /// to copy e.g. status flag register classes.
94 int getCopyCost() const { return CopyCost; }
96 /// isAllocatable - Return true if this register class may be used to create
97 /// virtual registers.
98 bool isAllocatable() const { return Allocatable; }
101 /// MCRegisterDesc - This record contains all of the information known about
102 /// a particular register. The Overlaps field contains a pointer to a zero
103 /// terminated array of registers that this register aliases, starting with
104 /// itself. This is needed for architectures like X86 which have AL alias AX
105 /// alias EAX. The SubRegs field is a zero terminated array of registers that
106 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
107 /// AX. The SuperRegs field is a zero terminated array of registers that are
108 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
111 struct MCRegisterDesc {
112 const char *Name; // Printable name for the reg (for debugging)
113 const unsigned *Overlaps; // Overlapping registers, described above
114 const unsigned *SubRegs; // Sub-register set, described above
115 const unsigned *SuperRegs; // Super-register set, described above
118 /// MCRegisterInfo base class - We assume that the target defines a static
119 /// array of MCRegisterDesc objects that represent all of the machine
120 /// registers that the target has. As such, we simply have to track a pointer
121 /// to this array so that we can turn register number into a register
124 /// Note this class is designed to be a base class of TargetRegisterInfo, which
125 /// is the interface used by codegen. However, specific targets *should never*
126 /// specialize this class. MCRegisterInfo should only contain getters to access
127 /// TableGen generated physical register data. It must not be extended with
130 class MCRegisterInfo {
132 const MCRegisterDesc *Desc; // Pointer to the descriptor array
133 unsigned NumRegs; // Number of entries in the array
134 unsigned RAReg; // Return address register
135 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
136 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
137 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
138 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
139 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
142 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
143 /// auto-generated routines. *DO NOT USE*.
144 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA) {
150 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
151 /// register number mapping. Called by TableGen auto-generated routines.
153 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
155 EHL2DwarfRegs[LLVMReg] = DwarfReg;
157 L2DwarfRegs[LLVMReg] = DwarfReg;
160 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
161 /// register number mapping. Called by TableGen auto-generated routines.
163 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
165 EHDwarf2LRegs[DwarfReg] = LLVMReg;
167 Dwarf2LRegs[DwarfReg] = LLVMReg;
170 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
171 /// number mapping. By default the SEH register number is just the same
172 /// as the LLVM register number.
173 /// FIXME: TableGen these numbers. Currently this requires target specific
174 /// initialization code.
175 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
176 L2SEHRegs[LLVMReg] = SEHReg;
179 /// getRARegister - This method should return the register where the return
180 /// address can be found.
181 unsigned getRARegister() const {
185 const MCRegisterDesc &operator[](unsigned RegNo) const {
186 assert(RegNo < NumRegs &&
187 "Attempting to access record for invalid register number!");
191 /// Provide a get method, equivalent to [], but more useful if we have a
192 /// pointer to this object.
194 const MCRegisterDesc &get(unsigned RegNo) const {
195 return operator[](RegNo);
198 /// getAliasSet - Return the set of registers aliased by the specified
199 /// register, or a null list of there are none. The list returned is zero
202 const unsigned *getAliasSet(unsigned RegNo) const {
203 // The Overlaps set always begins with Reg itself.
204 return get(RegNo).Overlaps + 1;
207 /// getOverlaps - Return a list of registers that overlap Reg, including
208 /// itself. This is the same as the alias set except Reg is included in the
210 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
212 const unsigned *getOverlaps(unsigned RegNo) const {
213 return get(RegNo).Overlaps;
216 /// getSubRegisters - Return the list of registers that are sub-registers of
217 /// the specified register, or a null list of there are none. The list
218 /// returned is zero terminated and sorted according to super-sub register
219 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
221 const unsigned *getSubRegisters(unsigned RegNo) const {
222 return get(RegNo).SubRegs;
225 /// getSuperRegisters - Return the list of registers that are super-registers
226 /// of the specified register, or a null list of there are none. The list
227 /// returned is zero terminated and sorted according to super-sub register
228 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
230 const unsigned *getSuperRegisters(unsigned RegNo) const {
231 return get(RegNo).SuperRegs;
234 /// getName - Return the human-readable symbolic target-specific name for the
235 /// specified physical register.
236 const char *getName(unsigned RegNo) const {
237 return get(RegNo).Name;
240 /// getNumRegs - Return the number of registers this target has (useful for
241 /// sizing arrays holding per register information)
242 unsigned getNumRegs() const {
246 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
247 /// number. Returns -1 if there is no equivalent value. The second
248 /// parameter allows targets to use different numberings for EH info and
250 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
251 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
252 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
253 if (I == M.end()) return -1;
257 /// getLLVMRegNum - Map a dwarf register back to a target register.
259 int getLLVMRegNum(unsigned RegNum, bool isEH) const {
260 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
261 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
263 assert(0 && "Invalid RegNum");
269 /// getSEHRegNum - Map a target register to an equivalent SEH register
270 /// number. Returns LLVM register number if there is no equivalent value.
271 int getSEHRegNum(unsigned RegNum) const {
272 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
273 if (I == L2SEHRegs.end()) return (int)RegNum;
278 } // End llvm namespace