1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// MCRegisterClass - Base class of TargetRegisterClass.
26 class MCRegisterClass {
28 typedef const uint16_t* iterator;
29 typedef const uint16_t* const_iterator;
32 const iterator RegsBegin;
33 const uint8_t *const RegSet;
34 const uint16_t RegsSize;
35 const uint16_t RegSetSize;
37 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
38 const int8_t CopyCost;
39 const bool Allocatable;
41 /// getID() - Return the register class ID number.
43 unsigned getID() const { return ID; }
45 /// getName() - Return the register class name for debugging.
47 const char *getName() const { return Name; }
49 /// begin/end - Return all of the registers in this class.
51 iterator begin() const { return RegsBegin; }
52 iterator end() const { return RegsBegin + RegsSize; }
54 /// getNumRegs - Return the number of registers in this class.
56 unsigned getNumRegs() const { return RegsSize; }
58 /// getRegister - Return the specified register in the class.
60 unsigned getRegister(unsigned i) const {
61 assert(i < getNumRegs() && "Register number out of range!");
65 /// contains - Return true if the specified register is included in this
66 /// register class. This does not include virtual registers.
67 bool contains(unsigned Reg) const {
68 unsigned InByte = Reg % 8;
69 unsigned Byte = Reg / 8;
70 if (Byte >= RegSetSize)
72 return (RegSet[Byte] & (1 << InByte)) != 0;
75 /// contains - Return true if both registers are in this class.
76 bool contains(unsigned Reg1, unsigned Reg2) const {
77 return contains(Reg1) && contains(Reg2);
80 /// getSize - Return the size of the register in bytes, which is also the size
81 /// of a stack slot allocated to hold a spilled copy of this register.
82 unsigned getSize() const { return RegSize; }
84 /// getAlignment - Return the minimum required alignment for a register of
86 unsigned getAlignment() const { return Alignment; }
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost; }
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable; }
98 /// MCRegisterDesc - This record contains all of the information known about
99 /// a particular register. The Overlaps field contains a pointer to a zero
100 /// terminated array of registers that this register aliases, starting with
101 /// itself. This is needed for architectures like X86 which have AL alias AX
102 /// alias EAX. The SubRegs field is a zero terminated array of registers that
103 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
104 /// AX. The SuperRegs field is a zero terminated array of registers that are
105 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
108 struct MCRegisterDesc {
109 uint32_t Name; // Printable name for the reg (for debugging)
110 uint32_t Overlaps; // Overlapping registers, described above
111 uint32_t SubRegs; // Sub-register set, described above
112 uint32_t SuperRegs; // Super-register set, described above
114 // RegUnits - Points to the list of register units. The low 4 bits holds the
115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
119 /// MCRegisterInfo base class - We assume that the target defines a static
120 /// array of MCRegisterDesc objects that represent all of the machine
121 /// registers that the target has. As such, we simply have to track a pointer
122 /// to this array so that we can turn register number into a register
125 /// Note this class is designed to be a base class of TargetRegisterInfo, which
126 /// is the interface used by codegen. However, specific targets *should never*
127 /// specialize this class. MCRegisterInfo should only contain getters to access
128 /// TableGen generated physical register data. It must not be extended with
131 class MCRegisterInfo {
133 typedef const MCRegisterClass *regclass_iterator;
135 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
136 /// performed with a binary search.
137 struct DwarfLLVMRegPair {
141 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
144 const MCRegisterDesc *Desc; // Pointer to the descriptor array
145 unsigned NumRegs; // Number of entries in the array
146 unsigned RAReg; // Return address register
147 const MCRegisterClass *Classes; // Pointer to the regclass array
148 unsigned NumClasses; // Number of entries in the array
149 unsigned NumRegUnits; // Number of regunits.
150 const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
151 const uint16_t *RegLists; // Pointer to the reglists array
152 const uint16_t *DiffLists; // Pointer to the difflists array
153 const char *RegStrings; // Pointer to the string table.
154 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
156 unsigned NumSubRegIndices; // Number of subreg indices.
157 const uint16_t *RegEncodingTable; // Pointer to array of register
160 unsigned L2DwarfRegsSize;
161 unsigned EHL2DwarfRegsSize;
162 unsigned Dwarf2LRegsSize;
163 unsigned EHDwarf2LRegsSize;
164 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
165 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
166 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
167 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
168 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
171 /// RegListIterator. This iterator class is used to traverse lists of
172 /// super-registers, sub-registers, and overlapping registers. Don't use it
173 /// directly, use one of the sub-classes defined below.
174 class RegListIterator {
177 explicit RegListIterator(const uint16_t *Table)
180 /// isValid - Return false when the end of the list is reached.
181 bool isValid() const { return *Pos; }
183 /// Dereference the iterator to get the current register.
184 unsigned operator*() const { return *Pos; }
186 /// Pre-increment. Move to the next register.
187 void operator++() { ++Pos; }
190 /// DiffListIterator - Base iterator class that can traverse the
191 /// differentially encoded register and regunit lists in DiffLists.
192 /// Don't use this class directly, use one of the specialized sub-classes
194 class DiffListIterator {
196 const uint16_t *List;
199 /// Create an invalid iterator. Call init() to point to something useful.
200 DiffListIterator() : Val(0), List(0) {}
202 /// init - Point the iterator to InitVal, decoding subsequent values from
203 /// DiffList. The iterator will initially point to InitVal, sub-classes are
204 /// responsible for skipping the seed value if it is not part of the list.
205 void init(uint16_t InitVal, const uint16_t *DiffList) {
210 /// advance - Move to the next list position, return the applied
211 /// differential. This function does not detect the end of the list, that
212 /// is the caller's responsibility (by checking for a 0 return value).
214 assert(isValid() && "Cannot move off the end of the list.");
215 uint16_t D = *List++;
222 /// isValid - returns true if this iterator is not yet at the end.
223 bool isValid() const { return List; }
225 /// Dereference the iterator to get the value at the current position.
226 unsigned operator*() const { return Val; }
228 /// Pre-increment to move to the next position.
230 // The end of the list is encoded as a 0 differential.
236 // These iterators are allowed to sub-class RegListIterator and
237 // DiffListIterator and access internal list pointers.
238 friend class MCSubRegIterator;
239 friend class MCSuperRegIterator;
240 friend class MCRegAliasIterator;
241 friend class MCRegUnitIterator;
242 friend class MCRegUnitRootIterator;
244 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
245 /// auto-generated routines. *DO NOT USE*.
246 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
247 const MCRegisterClass *C, unsigned NC,
248 const uint16_t (*RURoots)[2],
253 const uint16_t *SubIndices,
255 const uint16_t *RET) {
262 RegStrings = Strings;
264 RegUnitRoots = RURoots;
266 SubRegIndices = SubIndices;
267 NumSubRegIndices = NumIndices;
268 RegEncodingTable = RET;
271 /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf
272 /// register number mapping. Called by TableGen auto-generated routines.
274 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
278 EHL2DwarfRegsSize = Size;
281 L2DwarfRegsSize = Size;
285 /// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM
286 /// register number mapping. Called by TableGen auto-generated routines.
288 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
292 EHDwarf2LRegsSize = Size;
295 Dwarf2LRegsSize = Size;
299 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
300 /// number mapping. By default the SEH register number is just the same
301 /// as the LLVM register number.
302 /// FIXME: TableGen these numbers. Currently this requires target specific
303 /// initialization code.
304 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
305 L2SEHRegs[LLVMReg] = SEHReg;
308 /// getRARegister - This method should return the register where the return
309 /// address can be found.
310 unsigned getRARegister() const {
314 const MCRegisterDesc &operator[](unsigned RegNo) const {
315 assert(RegNo < NumRegs &&
316 "Attempting to access record for invalid register number!");
320 /// Provide a get method, equivalent to [], but more useful if we have a
321 /// pointer to this object.
323 const MCRegisterDesc &get(unsigned RegNo) const {
324 return operator[](RegNo);
327 /// getAliasSet - Return the set of registers aliased by the specified
328 /// register, or a null list of there are none. The list returned is zero
331 const uint16_t *getAliasSet(unsigned RegNo) const {
332 // The Overlaps set always begins with Reg itself.
333 return RegLists + get(RegNo).Overlaps + 1;
336 /// getOverlaps - Return a list of registers that overlap Reg, including
337 /// itself. This is the same as the alias set except Reg is included in the
339 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
341 const uint16_t *getOverlaps(unsigned RegNo) const {
342 return RegLists + get(RegNo).Overlaps;
345 /// getSubRegisters - Return the list of registers that are sub-registers of
346 /// the specified register, or a null list of there are none. The list
347 /// returned is zero terminated and sorted according to super-sub register
348 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
350 const uint16_t *getSubRegisters(unsigned RegNo) const {
351 return RegLists + get(RegNo).SubRegs;
354 /// getSubReg - Returns the physical register number of sub-register "Index"
355 /// for physical register RegNo. Return zero if the sub-register does not
357 unsigned getSubReg(unsigned Reg, unsigned Idx) const {
358 return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1);
361 /// getMatchingSuperReg - Return a super-register of the specified register
362 /// Reg so its sub-register of index SubIdx is Reg.
363 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
364 const MCRegisterClass *RC) const {
365 for (const uint16_t *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
366 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
371 /// getSubRegIndex - For a given register pair, return the sub-register index
372 /// if the second register is a sub-register of the first. Return zero
374 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {
375 for (unsigned I = 1; I <= NumSubRegIndices; ++I)
376 if (getSubReg(RegNo, I) == SubRegNo)
381 /// getSuperRegisters - Return the list of registers that are super-registers
382 /// of the specified register, or a null list of there are none. The list
383 /// returned is zero terminated and sorted according to super-sub register
384 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
386 const uint16_t *getSuperRegisters(unsigned RegNo) const {
387 return RegLists + get(RegNo).SuperRegs;
390 /// getName - Return the human-readable symbolic target-specific name for the
391 /// specified physical register.
392 const char *getName(unsigned RegNo) const {
393 return RegStrings + get(RegNo).Name;
396 /// getNumRegs - Return the number of registers this target has (useful for
397 /// sizing arrays holding per register information)
398 unsigned getNumRegs() const {
402 /// getNumRegUnits - Return the number of (native) register units in the
403 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
404 /// can be accessed through MCRegUnitIterator defined below.
405 unsigned getNumRegUnits() const {
409 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
410 /// number. Returns -1 if there is no equivalent value. The second
411 /// parameter allows targets to use different numberings for EH info and
413 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
414 const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
415 unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
417 DwarfLLVMRegPair Key = { RegNum, 0 };
418 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
419 if (I == M+Size || I->FromReg != RegNum)
424 /// getLLVMRegNum - Map a dwarf register back to a target register.
426 int getLLVMRegNum(unsigned RegNum, bool isEH) const {
427 const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
428 unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
430 DwarfLLVMRegPair Key = { RegNum, 0 };
431 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
432 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum");
436 /// getSEHRegNum - Map a target register to an equivalent SEH register
437 /// number. Returns LLVM register number if there is no equivalent value.
438 int getSEHRegNum(unsigned RegNum) const {
439 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
440 if (I == L2SEHRegs.end()) return (int)RegNum;
444 regclass_iterator regclass_begin() const { return Classes; }
445 regclass_iterator regclass_end() const { return Classes+NumClasses; }
447 unsigned getNumRegClasses() const {
448 return (unsigned)(regclass_end()-regclass_begin());
451 /// getRegClass - Returns the register class associated with the enumeration
452 /// value. See class MCOperandInfo.
453 const MCRegisterClass getRegClass(unsigned i) const {
454 assert(i < getNumRegClasses() && "Register Class ID out of range");
458 /// getEncodingValue - Returns the encoding for RegNo
459 uint16_t getEncodingValue(unsigned RegNo) const {
460 assert(RegNo < NumRegs &&
461 "Attempting to get encoding for invalid register number!");
462 return RegEncodingTable[RegNo];
467 //===----------------------------------------------------------------------===//
468 // Register List Iterators
469 //===----------------------------------------------------------------------===//
471 // MCRegisterInfo provides lists of super-registers, sub-registers, and
472 // aliasing registers. Use these iterator classes to traverse the lists.
474 /// MCSubRegIterator enumerates all sub-registers of Reg.
475 class MCSubRegIterator : public MCRegisterInfo::RegListIterator {
477 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI)
478 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).SubRegs) {}
481 /// MCSuperRegIterator enumerates all super-registers of Reg.
482 class MCSuperRegIterator : public MCRegisterInfo::RegListIterator {
484 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI)
485 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).SuperRegs) {}
488 /// MCRegAliasIterator enumerates all registers aliasing Reg.
489 /// If IncludeSelf is set, Reg itself is included in the list.
490 class MCRegAliasIterator : public MCRegisterInfo::RegListIterator {
492 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf)
493 : RegListIterator(MCRI->RegLists + MCRI->get(Reg).Overlaps + !IncludeSelf)
497 //===----------------------------------------------------------------------===//
499 //===----------------------------------------------------------------------===//
501 // Register units are used to compute register aliasing. Every register has at
502 // least one register unit, but it can have more. Two registers overlap if and
503 // only if they have a common register unit.
505 // A target with a complicated sub-register structure will typically have many
506 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
507 // the number of register units in the target.
509 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
510 // in ascending numerical order.
511 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
513 /// MCRegUnitIterator - Create an iterator that traverses the register units
515 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
516 // Decode the RegUnits MCRegisterDesc field.
517 unsigned RU = MCRI->get(Reg).RegUnits;
518 unsigned Scale = RU & 15;
519 unsigned Offset = RU >> 4;
521 // Initialize the iterator to Reg * Scale, and the List pointer to
522 // DiffLists + Offset.
523 init(Reg * Scale, MCRI->DiffLists + Offset);
525 // That may not be a valid unit, we need to advance by one to get the real
526 // unit number. The first differential can be 0 which would normally
527 // terminate the list, but since we know every register has at least one
528 // unit, we can allow a 0 differential here.
533 // Each register unit has one or two root registers. The complete set of
534 // registers containing a register unit is the union of the roots and their
535 // super-registers. All registers aliasing Unit can be visited like this:
537 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
538 // unsigned Root = *RI;
540 // for (MCSuperRegIterator SI(Root, MCRI); SI.isValid(); ++SI)
544 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
545 class MCRegUnitRootIterator {
549 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
550 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
551 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
552 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
555 /// Dereference to get the current root register.
556 unsigned operator*() const {
560 /// isValid - Check if the iterator is at the end of the list.
561 bool isValid() const {
565 /// Preincrement to move to the next root register.
567 assert(isValid() && "Cannot move off the end of the list.");
573 } // End llvm namespace