1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/DenseSet.h"
25 /// MCRegisterClass - Base class of TargetRegisterClass.
26 class MCRegisterClass {
28 typedef const unsigned* iterator;
29 typedef const unsigned* const_iterator;
33 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
35 const bool Allocatable;
36 const iterator RegsBegin, RegsEnd;
37 DenseSet<unsigned> RegSet;
39 MCRegisterClass(unsigned id, const char *name,
40 unsigned RS, unsigned Al, int CC, bool Allocable,
41 iterator RB, iterator RE)
42 : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
43 Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {}
45 /// initMCRegisterClass - Initialize initMCRegisterClass. *DO NOT USE*.
46 // FIXME: This could go away if RegSet would use a constant bit field.
47 void initMCRegisterClass() {
48 RegSet.resize(getNumRegs());
49 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
53 /// getID() - Return the register class ID number.
55 unsigned getID() const { return ID; }
57 /// getName() - Return the register class name for debugging.
59 const char *getName() const { return Name; }
61 /// begin/end - Return all of the registers in this class.
63 iterator begin() const { return RegsBegin; }
64 iterator end() const { return RegsEnd; }
66 /// getNumRegs - Return the number of registers in this class.
68 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
70 /// getRegister - Return the specified register in the class.
72 unsigned getRegister(unsigned i) const {
73 assert(i < getNumRegs() && "Register number out of range!");
77 /// contains - Return true if the specified register is included in this
78 /// register class. This does not include virtual registers.
79 bool contains(unsigned Reg) const {
80 return RegSet.count(Reg);
83 /// contains - Return true if both registers are in this class.
84 bool contains(unsigned Reg1, unsigned Reg2) const {
85 return contains(Reg1) && contains(Reg2);
88 /// getSize - Return the size of the register in bytes, which is also the size
89 /// of a stack slot allocated to hold a spilled copy of this register.
90 unsigned getSize() const { return RegSize; }
92 /// getAlignment - Return the minimum required alignment for a register of
94 unsigned getAlignment() const { return Alignment; }
96 /// getCopyCost - Return the cost of copying a value between two registers in
97 /// this class. A negative number means the register class is very expensive
98 /// to copy e.g. status flag register classes.
99 int getCopyCost() const { return CopyCost; }
101 /// isAllocatable - Return true if this register class may be used to create
102 /// virtual registers.
103 bool isAllocatable() const { return Allocatable; }
106 /// MCRegisterDesc - This record contains all of the information known about
107 /// a particular register. The Overlaps field contains a pointer to a zero
108 /// terminated array of registers that this register aliases, starting with
109 /// itself. This is needed for architectures like X86 which have AL alias AX
110 /// alias EAX. The SubRegs field is a zero terminated array of registers that
111 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
112 /// AX. The SuperRegs field is a zero terminated array of registers that are
113 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
116 struct MCRegisterDesc {
117 const char *Name; // Printable name for the reg (for debugging)
118 const unsigned *Overlaps; // Overlapping registers, described above
119 const unsigned *SubRegs; // Sub-register set, described above
120 const unsigned *SuperRegs; // Super-register set, described above
123 /// MCRegisterInfo base class - We assume that the target defines a static
124 /// array of MCRegisterDesc objects that represent all of the machine
125 /// registers that the target has. As such, we simply have to track a pointer
126 /// to this array so that we can turn register number into a register
129 /// Note this class is designed to be a base class of TargetRegisterInfo, which
130 /// is the interface used by codegen. However, specific targets *should never*
131 /// specialize this class. MCRegisterInfo should only contain getters to access
132 /// TableGen generated physical register data. It must not be extended with
135 class MCRegisterInfo {
137 typedef const MCRegisterClass *regclass_iterator;
139 const MCRegisterDesc *Desc; // Pointer to the descriptor array
140 unsigned NumRegs; // Number of entries in the array
141 unsigned RAReg; // Return address register
142 const MCRegisterClass *Classes; // Pointer to the regclass array
143 unsigned NumClasses; // Number of entries in the array
144 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
145 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
146 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
147 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
148 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
151 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
152 /// auto-generated routines. *DO NOT USE*.
153 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
154 MCRegisterClass *C, unsigned NC) {
160 // FIXME: This should go away.
161 for (unsigned i = 0; i != NC; ++i)
162 C[i].initMCRegisterClass();
165 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
166 /// register number mapping. Called by TableGen auto-generated routines.
168 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
170 EHL2DwarfRegs[LLVMReg] = DwarfReg;
172 L2DwarfRegs[LLVMReg] = DwarfReg;
175 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
176 /// register number mapping. Called by TableGen auto-generated routines.
178 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
180 EHDwarf2LRegs[DwarfReg] = LLVMReg;
182 Dwarf2LRegs[DwarfReg] = LLVMReg;
185 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
186 /// number mapping. By default the SEH register number is just the same
187 /// as the LLVM register number.
188 /// FIXME: TableGen these numbers. Currently this requires target specific
189 /// initialization code.
190 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
191 L2SEHRegs[LLVMReg] = SEHReg;
194 /// getRARegister - This method should return the register where the return
195 /// address can be found.
196 unsigned getRARegister() const {
200 const MCRegisterDesc &operator[](unsigned RegNo) const {
201 assert(RegNo < NumRegs &&
202 "Attempting to access record for invalid register number!");
206 /// Provide a get method, equivalent to [], but more useful if we have a
207 /// pointer to this object.
209 const MCRegisterDesc &get(unsigned RegNo) const {
210 return operator[](RegNo);
213 /// getAliasSet - Return the set of registers aliased by the specified
214 /// register, or a null list of there are none. The list returned is zero
217 const unsigned *getAliasSet(unsigned RegNo) const {
218 // The Overlaps set always begins with Reg itself.
219 return get(RegNo).Overlaps + 1;
222 /// getOverlaps - Return a list of registers that overlap Reg, including
223 /// itself. This is the same as the alias set except Reg is included in the
225 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
227 const unsigned *getOverlaps(unsigned RegNo) const {
228 return get(RegNo).Overlaps;
231 /// getSubRegisters - Return the list of registers that are sub-registers of
232 /// the specified register, or a null list of there are none. The list
233 /// returned is zero terminated and sorted according to super-sub register
234 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
236 const unsigned *getSubRegisters(unsigned RegNo) const {
237 return get(RegNo).SubRegs;
240 /// getSuperRegisters - Return the list of registers that are super-registers
241 /// of the specified register, or a null list of there are none. The list
242 /// returned is zero terminated and sorted according to super-sub register
243 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
245 const unsigned *getSuperRegisters(unsigned RegNo) const {
246 return get(RegNo).SuperRegs;
249 /// getName - Return the human-readable symbolic target-specific name for the
250 /// specified physical register.
251 const char *getName(unsigned RegNo) const {
252 return get(RegNo).Name;
255 /// getNumRegs - Return the number of registers this target has (useful for
256 /// sizing arrays holding per register information)
257 unsigned getNumRegs() const {
261 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
262 /// number. Returns -1 if there is no equivalent value. The second
263 /// parameter allows targets to use different numberings for EH info and
265 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
266 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
267 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
268 if (I == M.end()) return -1;
272 /// getLLVMRegNum - Map a dwarf register back to a target register.
274 int getLLVMRegNum(unsigned RegNum, bool isEH) const {
275 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
276 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
278 assert(0 && "Invalid RegNum");
284 /// getSEHRegNum - Map a target register to an equivalent SEH register
285 /// number. Returns LLVM register number if there is no equivalent value.
286 int getSEHRegNum(unsigned RegNum) const {
287 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
288 if (I == L2SEHRegs.end()) return (int)RegNum;
292 regclass_iterator regclass_begin() const { return Classes; }
293 regclass_iterator regclass_end() const { return Classes+NumClasses; }
295 unsigned getNumRegClasses() const {
296 return (unsigned)(regclass_end()-regclass_begin());
299 /// getRegClass - Returns the register class associated with the enumeration
300 /// value. See class MCOperandInfo.
301 const MCRegisterClass getRegClass(unsigned i) const {
302 assert(i < getNumRegClasses() && "Register Class ID out of range");
307 } // End llvm namespace