1 //===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the classes used to describe a subtarget's machine model
11 // for scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCSCHEDULE_H
16 #define LLVM_MC_MCSCHEDULE_H
18 #include "llvm/Support/DataTypes.h"
23 struct InstrItinerary;
25 /// Define a kind of processor resource that will be modeled by the scheduler.
26 struct MCProcResourceDesc {
30 unsigned NumUnits; // Number of resource of this kind
31 unsigned SuperIdx; // Index of the resources kind that contains this kind.
33 // Buffered resources may be consumed at some indeterminate cycle after
34 // dispatch (e.g. for instructions that may issue out-of-order). Unbuffered
35 // resources always consume their resource some fixed number of cycles after
36 // dispatch (e.g. for instruction interlocking that may stall the pipeline).
39 bool operator==(const MCProcResourceDesc &Other) const {
40 return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
41 && IsBuffered == Other.IsBuffered;
45 /// Identify one of the processor resource kinds consumed by a particular
46 /// scheduling class for the specified number of cycles.
47 struct MCWriteProcResEntry {
48 unsigned ProcResourceIdx;
51 bool operator==(const MCWriteProcResEntry &Other) const {
52 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
56 /// Specify the latency in cpu cycles for a particular scheduling class and def
57 /// index. -1 indicates an invalid latency. Heuristics would typically consider
58 /// an instruction with invalid latency to have infinite latency. Also identify
59 /// the WriteResources of this def. When the operand expands to a sequence of
60 /// writes, this ID is the last write in the sequence.
61 struct MCWriteLatencyEntry {
63 unsigned WriteResourceID;
65 bool operator==(const MCWriteLatencyEntry &Other) const {
66 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
70 /// Specify the number of cycles allowed after instruction issue before a
71 /// particular use operand reads its registers. This effectively reduces the
72 /// write's latency. Here we allow negative cycles for corner cases where
73 /// latency increases. This rule only applies when the entry's WriteResource
74 /// matches the write's WriteResource.
76 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
78 struct MCReadAdvanceEntry {
80 unsigned WriteResourceID;
83 bool operator==(const MCReadAdvanceEntry &Other) const {
84 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
85 && Cycles == Other.Cycles;
89 /// Summarize the scheduling resources required for an instruction of a
90 /// particular scheduling class.
92 /// Defined as an aggregate struct for creating tables with initializer lists.
93 struct MCSchedClassDesc {
94 static const unsigned short InvalidNumMicroOps = UINT16_MAX;
95 static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
100 unsigned short NumMicroOps;
103 unsigned WriteProcResIdx; // First index into WriteProcResTable.
104 unsigned NumWriteProcResEntries;
105 unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
106 unsigned NumWriteLatencyEntries;
107 unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable.
108 unsigned NumReadAdvanceEntries;
110 bool isValid() const {
111 return NumMicroOps != InvalidNumMicroOps;
113 bool isVariant() const {
114 return NumMicroOps == VariantNumMicroOps;
118 /// Machine model for scheduling, bundling, and heuristics.
120 /// The machine model directly provides basic information about the
121 /// microarchitecture to the scheduler in the form of properties. It also
122 /// optionally refers to scheduler resource tables and itinerary
123 /// tables. Scheduler resource tables model the latency and cost for each
124 /// instruction type. Itinerary tables are an independant mechanism that
125 /// provides a detailed reservation table describing each cycle of instruction
126 /// execution. Subtargets may define any or all of the above categories of data
127 /// depending on the type of CPU and selected scheduler.
130 static MCSchedModel DefaultSchedModel; // For unknown processors.
132 // IssueWidth is the maximum number of instructions that may be scheduled in
133 // the same per-cycle group.
135 static const unsigned DefaultIssueWidth = 1;
137 // MinLatency is the minimum latency between a register write
138 // followed by a data dependent read. This determines which
139 // instructions may be scheduled in the same per-cycle group. This
140 // is distinct from *expected* latency, which determines the likely
141 // critical path but does not guarantee a pipeline
142 // hazard. MinLatency can always be overridden by the number of
143 // InstrStage cycles.
145 // (-1) Standard in-order processor.
146 // Use InstrItinerary OperandCycles as MinLatency.
147 // If no OperandCycles exist, then use the cycle of the last InstrStage.
149 // (0) Out-of-order processor, or in-order with bundled dependencies.
150 // RAW dependencies may be dispatched in the same cycle.
151 // Optional InstrItinerary OperandCycles provides expected latency.
153 // (>0) In-order processor with variable latencies.
154 // Use the greater of this value or the cycle of the last InstrStage.
155 // Optional InstrItinerary OperandCycles provides expected latency.
156 // TODO: can't yet specify both min and expected latency per operand.
158 static const int DefaultMinLatency = -1;
160 // LoadLatency is the expected latency of load instructions.
162 // If MinLatency >= 0, this may be overriden for individual load opcodes by
163 // InstrItinerary OperandCycles.
164 unsigned LoadLatency;
165 static const unsigned DefaultLoadLatency = 4;
167 // HighLatency is the expected latency of "very high latency" operations.
168 // See TargetInstrInfo::isHighLatencyDef().
169 // By default, this is set to an arbitrarily high number of cycles
170 // likely to have some impact on scheduling heuristics.
171 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
172 unsigned HighLatency;
173 static const unsigned DefaultHighLatency = 10;
175 // ILPWindow is the number of cycles that the scheduler effectively ignores
176 // before attempting to hide latency. This should be zero for in-order cpus to
177 // always hide expected latency. For out-of-order cpus, it may be tweaked as
178 // desired to roughly approximate instruction buffers. The actual threshold is
179 // not very important for an OOO processor, as long as it isn't too high. A
180 // nonzero value helps avoid rescheduling to hide latency when its is fairly
181 // obviously useless and makes register pressure heuristics more effective.
183 static const unsigned DefaultILPWindow = 0;
185 // MispredictPenalty is the typical number of extra cycles the processor
186 // takes to recover from a branch misprediction.
187 unsigned MispredictPenalty;
188 static const unsigned DefaultMispredictPenalty = 10;
192 const MCProcResourceDesc *ProcResourceTable;
193 const MCSchedClassDesc *SchedClassTable;
194 unsigned NumProcResourceKinds;
195 unsigned NumSchedClasses;
196 // Instruction itinerary tables used by InstrItineraryData.
197 friend class InstrItineraryData;
198 const InstrItinerary *InstrItineraries;
201 // Default's must be specified as static const literals so that tablegenerated
202 // target code can use it in static initializers. The defaults need to be
203 // initialized in this default ctor because some clients directly instantiate
204 // MCSchedModel instead of using a generated itinerary.
205 MCSchedModel(): IssueWidth(DefaultIssueWidth),
206 MinLatency(DefaultMinLatency),
207 LoadLatency(DefaultLoadLatency),
208 HighLatency(DefaultHighLatency),
209 ILPWindow(DefaultILPWindow),
210 MispredictPenalty(DefaultMispredictPenalty),
211 ProcID(0), ProcResourceTable(0), SchedClassTable(0),
212 NumProcResourceKinds(0), NumSchedClasses(0),
213 InstrItineraries(0) {
214 (void)NumProcResourceKinds;
215 (void)NumSchedClasses;
218 // Table-gen driven ctor.
219 MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned ilp,
220 unsigned mp, unsigned pi, const MCProcResourceDesc *pr,
221 const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
222 const InstrItinerary *ii):
223 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
224 ILPWindow(ilp), MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr),
225 SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc),
226 InstrItineraries(ii) {}
228 unsigned getProcessorID() const { return ProcID; }
230 /// Does this machine model include instruction-level scheduling.
231 bool hasInstrSchedModel() const { return SchedClassTable; }
233 unsigned getNumProcResourceKinds() const {
234 return NumProcResourceKinds;
237 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
238 assert(hasInstrSchedModel() && "No scheduling machine model");
240 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
241 return &ProcResourceTable[ProcResourceIdx];
244 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
245 assert(hasInstrSchedModel() && "No scheduling machine model");
247 assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
248 return &SchedClassTable[SchedClassIdx];
252 } // End llvm namespace