1 //===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the classes used to describe a subtarget's machine model
11 // for scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCSCHEDMODEL_H
16 #define LLVM_MC_MCSCHEDMODEL_H
18 #include "llvm/Support/DataTypes.h"
23 struct InstrItinerary;
25 /// Define a kind of processor resource that will be modeled by the scheduler.
26 struct MCProcResourceDesc {
30 unsigned Count; // Number of resource of this kind
31 unsigned SuperIdx; // Index of the resources kind that contains this kind.
33 bool operator==(const MCProcResourceDesc &Other) const {
34 return Count == Other.Count && SuperIdx == Other.SuperIdx;
38 /// Identify one of the processor resource kinds consumed by a particular
39 /// scheduling class for the specified number of cycles.
40 struct MCWriteProcResEntry {
41 unsigned ProcResourceIdx;
44 bool operator==(const MCWriteProcResEntry &Other) const {
45 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
49 /// Specify the latency in cpu cycles for a particular scheduling class and def
50 /// index. Also identify the WriteResources of this def. When the operand
51 /// expands to a sequence of writes, this ID is the last write in the sequence.
52 struct MCWriteLatencyEntry {
54 unsigned WriteResourceID;
56 bool operator==(const MCWriteLatencyEntry &Other) const {
57 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
61 /// Specify the number of cycles allowed after instruction issue before a
62 /// particular use operand reads its registers. This effectively reduces the
63 /// write's latency. Here we allow negative cycles for corner cases where
64 /// latency increases. This rule only applies when the entry's WriteResource
65 /// matches the write's WriteResource.
67 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
69 struct MCReadAdvanceEntry {
71 unsigned WriteResourceID;
74 bool operator==(const MCReadAdvanceEntry &Other) const {
75 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
76 && Cycles == Other.Cycles;
80 /// Summarize the scheduling resources required for an instruction of a
81 /// particular scheduling class.
83 /// Defined as an aggregate struct for creating tables with initializer lists.
84 struct MCSchedClassDesc {
85 static const unsigned short InvalidNumMicroOps = UINT16_MAX;
86 static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
91 unsigned short NumMicroOps;
94 unsigned WriteProcResIdx; // First index into WriteProcResTable.
95 unsigned NumWriteProcResEntries;
96 unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
97 unsigned NumWriteLatencyEntries;
98 unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable.
99 unsigned NumReadAdvanceEntries;
101 bool isValid() const {
102 return NumMicroOps != InvalidNumMicroOps;
104 bool isVariant() const {
105 return NumMicroOps == VariantNumMicroOps;
109 /// Machine model for scheduling, bundling, and heuristics.
111 /// The machine model directly provides basic information about the
112 /// microarchitecture to the scheduler in the form of properties. It also
113 /// optionally refers to scheduler resource tables and itinerary
114 /// tables. Scheduler resource tables model the latency and cost for each
115 /// instruction type. Itinerary tables are an independant mechanism that
116 /// provides a detailed reservation table describing each cycle of instruction
117 /// execution. Subtargets may define any or all of the above categories of data
118 /// depending on the type of CPU and selected scheduler.
121 static MCSchedModel DefaultSchedModel; // For unknown processors.
123 // IssueWidth is the maximum number of instructions that may be scheduled in
124 // the same per-cycle group.
126 static const unsigned DefaultIssueWidth = 1;
128 // MinLatency is the minimum latency between a register write
129 // followed by a data dependent read. This determines which
130 // instructions may be scheduled in the same per-cycle group. This
131 // is distinct from *expected* latency, which determines the likely
132 // critical path but does not guarantee a pipeline
133 // hazard. MinLatency can always be overridden by the number of
134 // InstrStage cycles.
136 // (-1) Standard in-order processor.
137 // Use InstrItinerary OperandCycles as MinLatency.
138 // If no OperandCycles exist, then use the cycle of the last InstrStage.
140 // (0) Out-of-order processor, or in-order with bundled dependencies.
141 // RAW dependencies may be dispatched in the same cycle.
142 // Optional InstrItinerary OperandCycles provides expected latency.
144 // (>0) In-order processor with variable latencies.
145 // Use the greater of this value or the cycle of the last InstrStage.
146 // Optional InstrItinerary OperandCycles provides expected latency.
147 // TODO: can't yet specify both min and expected latency per operand.
149 static const unsigned DefaultMinLatency = -1;
151 // LoadLatency is the expected latency of load instructions.
153 // If MinLatency >= 0, this may be overriden for individual load opcodes by
154 // InstrItinerary OperandCycles.
155 unsigned LoadLatency;
156 static const unsigned DefaultLoadLatency = 4;
158 // HighLatency is the expected latency of "very high latency" operations.
159 // See TargetInstrInfo::isHighLatencyDef().
160 // By default, this is set to an arbitrarily high number of cycles
161 // likely to have some impact on scheduling heuristics.
162 // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
163 unsigned HighLatency;
164 static const unsigned DefaultHighLatency = 10;
166 // MispredictPenalty is the typical number of extra cycles the processor
167 // takes to recover from a branch misprediction.
168 unsigned MispredictPenalty;
169 static const unsigned DefaultMispredictPenalty = 10;
173 const MCProcResourceDesc *ProcResourceTable;
174 const MCSchedClassDesc *SchedClassTable;
176 unsigned NumProcResourceKinds;
177 unsigned NumSchedClasses;
179 // Instruction itinerary tables used by InstrItineraryData.
180 friend class InstrItineraryData;
181 const InstrItinerary *InstrItineraries;
184 // Default's must be specified as static const literals so that tablegenerated
185 // target code can use it in static initializers. The defaults need to be
186 // initialized in this default ctor because some clients directly instantiate
187 // MCSchedModel instead of using a generated itinerary.
188 MCSchedModel(): IssueWidth(DefaultIssueWidth),
189 MinLatency(DefaultMinLatency),
190 LoadLatency(DefaultLoadLatency),
191 HighLatency(DefaultHighLatency),
192 MispredictPenalty(DefaultMispredictPenalty),
193 ProcID(0), InstrItineraries(0) {}
195 // Table-gen driven ctor.
196 MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp,
197 const InstrItinerary *ii):
198 IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
199 MispredictPenalty(mp), ProcID(0), ProcResourceTable(0),
200 SchedClassTable(0), InstrItineraries(ii) {}
202 /// Does this machine model include instruction-level scheduling.
203 bool hasInstrSchedModel() const {
204 return SchedClassTable;
207 /// Does this machine model include cycle-to-cycle itineraries.
208 bool hasInstrItineraries() const {
209 return InstrItineraries;
212 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
213 assert(hasInstrSchedModel() && "No scheduling machine model");
215 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
216 return &ProcResourceTable[ProcResourceIdx];
219 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
220 assert(hasInstrSchedModel() && "No scheduling machine model");
222 assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
223 return &SchedClassTable[SchedClassIdx];
227 } // End llvm namespace