1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_MC_MCSUBTARGET_H
15 #define LLVM_MC_MCSUBTARGET_H
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/MC/SubtargetFeature.h"
25 //===----------------------------------------------------------------------===//
27 /// MCSubtargetInfo - Generic base class for all target subtargets.
29 class MCSubtargetInfo {
30 std::string TargetTriple; // Target triple
31 ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
32 ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
34 // Scheduler machine model
35 const SubtargetInfoKV *ProcSchedModels;
36 const MCWriteProcResEntry *WriteProcResTable;
37 const MCWriteLatencyEntry *WriteLatencyTable;
38 const MCReadAdvanceEntry *ReadAdvanceTable;
39 const MCSchedModel *CPUSchedModel;
41 const InstrStage *Stages; // Instruction itinerary stages
42 const unsigned *OperandCycles; // Itinerary operand cycles
43 const unsigned *ForwardingPaths; // Forwarding paths
44 uint64_t FeatureBits; // Feature bits for current CPU + FS
47 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
48 ArrayRef<SubtargetFeatureKV> PF,
49 ArrayRef<SubtargetFeatureKV> PD,
50 const SubtargetInfoKV *ProcSched,
51 const MCWriteProcResEntry *WPR,
52 const MCWriteLatencyEntry *WL,
53 const MCReadAdvanceEntry *RA,
55 const unsigned *OC, const unsigned *FP);
57 /// getTargetTriple - Return the target triple string.
58 StringRef getTargetTriple() const {
62 /// getFeatureBits - Return the feature bits.
64 uint64_t getFeatureBits() const {
68 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
69 /// feature string). Recompute feature bits and scheduling model.
70 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
72 /// InitCPUSchedModel - Recompute scheduling model based on CPU.
73 void InitCPUSchedModel(StringRef CPU);
75 /// ToggleFeature - Toggle a feature and returns the re-computed feature
76 /// bits. This version does not change the implied bits.
77 uint64_t ToggleFeature(uint64_t FB);
79 /// ToggleFeature - Toggle a feature and returns the re-computed feature
80 /// bits. This version will also change all implied bits.
81 uint64_t ToggleFeature(StringRef FS);
83 /// getSchedModelForCPU - Get the machine model of a CPU.
85 const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
87 /// getSchedModel - Get the machine model for this subtarget's CPU.
89 const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
91 /// Return an iterator at the first process resource consumed by the given
93 const MCWriteProcResEntry *getWriteProcResBegin(
94 const MCSchedClassDesc *SC) const {
95 return &WriteProcResTable[SC->WriteProcResIdx];
97 const MCWriteProcResEntry *getWriteProcResEnd(
98 const MCSchedClassDesc *SC) const {
99 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
102 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
103 unsigned DefIdx) const {
104 assert(DefIdx < SC->NumWriteLatencyEntries &&
105 "MachineModel does not specify a WriteResource for DefIdx");
107 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
110 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
111 unsigned WriteResID) const {
112 // TODO: The number of read advance entries in a class can be significant
113 // (~50). Consider compressing the WriteID into a dense ID of those that are
114 // used by ReadAdvance and representing them as a bitset.
115 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
116 *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
117 if (I->UseIdx < UseIdx)
119 if (I->UseIdx > UseIdx)
121 // Find the first WriteResIdx match, which has the highest cycle count.
122 if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
129 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
131 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
133 /// Initialize an InstrItineraryData instance.
134 void initInstrItins(InstrItineraryData &InstrItins) const;
137 } // End llvm namespace