1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/MC/SubtargetFeature.h"
25 //===----------------------------------------------------------------------===//
27 /// MCSubtargetInfo - Generic base class for all target subtargets.
29 class MCSubtargetInfo {
30 std::string TargetTriple; // Target triple
31 std::string CPU; // CPU being targeted.
32 ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
33 ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
35 // Scheduler machine model
36 const SubtargetInfoKV *ProcSchedModels;
37 const MCWriteProcResEntry *WriteProcResTable;
38 const MCWriteLatencyEntry *WriteLatencyTable;
39 const MCReadAdvanceEntry *ReadAdvanceTable;
40 MCSchedModel CPUSchedModel;
42 const InstrStage *Stages; // Instruction itinerary stages
43 const unsigned *OperandCycles; // Itinerary operand cycles
44 const unsigned *ForwardingPaths; // Forwarding paths
45 uint64_t FeatureBits; // Feature bits for current CPU + FS
48 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
49 ArrayRef<SubtargetFeatureKV> PF,
50 ArrayRef<SubtargetFeatureKV> PD,
51 const SubtargetInfoKV *ProcSched,
52 const MCWriteProcResEntry *WPR,
53 const MCWriteLatencyEntry *WL,
54 const MCReadAdvanceEntry *RA,
56 const unsigned *OC, const unsigned *FP);
58 /// getTargetTriple - Return the target triple string.
59 StringRef getTargetTriple() const {
63 /// getCPU - Return the CPU string.
64 StringRef getCPU() const {
68 /// getFeatureBits - Return the feature bits.
70 uint64_t getFeatureBits() const {
74 /// setFeatureBits - Set the feature bits.
76 void setFeatureBits(uint64_t FeatureBits_) { FeatureBits = FeatureBits_; }
78 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
79 /// feature string). Recompute feature bits and scheduling model.
80 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
82 /// InitCPUSchedModel - Recompute scheduling model based on CPU.
83 void InitCPUSchedModel(StringRef CPU);
85 /// ToggleFeature - Toggle a feature and returns the re-computed feature
86 /// bits. This version does not change the implied bits.
87 uint64_t ToggleFeature(uint64_t FB);
89 /// ToggleFeature - Toggle a feature and returns the re-computed feature
90 /// bits. This version will also change all implied bits.
91 uint64_t ToggleFeature(StringRef FS);
93 /// getSchedModelForCPU - Get the machine model of a CPU.
95 MCSchedModel getSchedModelForCPU(StringRef CPU) const;
97 /// getSchedModel - Get the machine model for this subtarget's CPU.
99 const MCSchedModel &getSchedModel() const { return CPUSchedModel; }
101 /// Return an iterator at the first process resource consumed by the given
102 /// scheduling class.
103 const MCWriteProcResEntry *getWriteProcResBegin(
104 const MCSchedClassDesc *SC) const {
105 return &WriteProcResTable[SC->WriteProcResIdx];
107 const MCWriteProcResEntry *getWriteProcResEnd(
108 const MCSchedClassDesc *SC) const {
109 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
112 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
113 unsigned DefIdx) const {
114 assert(DefIdx < SC->NumWriteLatencyEntries &&
115 "MachineModel does not specify a WriteResource for DefIdx");
117 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
120 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
121 unsigned WriteResID) const {
122 // TODO: The number of read advance entries in a class can be significant
123 // (~50). Consider compressing the WriteID into a dense ID of those that are
124 // used by ReadAdvance and representing them as a bitset.
125 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
126 *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
127 if (I->UseIdx < UseIdx)
129 if (I->UseIdx > UseIdx)
131 // Find the first WriteResIdx match, which has the highest cycle count.
132 if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
139 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
141 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
143 /// Initialize an InstrItineraryData instance.
144 void initInstrItins(InstrItineraryData &InstrItins) const;
146 /// Check whether the CPU string is valid.
147 bool isCPUStringValid(StringRef CPU) {
148 auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
149 [=](const SubtargetFeatureKV &KV) {
150 return CPU == KV.Key;
152 return Found != ProcDesc.end();
156 } // End llvm namespace