1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/MC/SubtargetFeature.h"
25 //===----------------------------------------------------------------------===//
27 /// MCSubtargetInfo - Generic base class for all target subtargets.
29 class MCSubtargetInfo {
30 Triple TargetTriple; // Target triple
31 std::string CPU; // CPU being targeted.
32 ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
33 ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
35 // Scheduler machine model
36 const SubtargetInfoKV *ProcSchedModels;
37 const MCWriteProcResEntry *WriteProcResTable;
38 const MCWriteLatencyEntry *WriteLatencyTable;
39 const MCReadAdvanceEntry *ReadAdvanceTable;
40 const MCSchedModel *CPUSchedModel;
42 const InstrStage *Stages; // Instruction itinerary stages
43 const unsigned *OperandCycles; // Itinerary operand cycles
44 const unsigned *ForwardingPaths; // Forwarding paths
45 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
47 MCSubtargetInfo() = delete;
48 MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
49 MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
52 MCSubtargetInfo(const MCSubtargetInfo &) = default;
53 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
54 ArrayRef<SubtargetFeatureKV> PF,
55 ArrayRef<SubtargetFeatureKV> PD,
56 const SubtargetInfoKV *ProcSched,
57 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
58 const MCReadAdvanceEntry *RA, const InstrStage *IS,
59 const unsigned *OC, const unsigned *FP);
61 /// getTargetTriple - Return the target triple string.
62 const Triple &getTargetTriple() const { return TargetTriple; }
64 /// getCPU - Return the CPU string.
65 StringRef getCPU() const {
69 /// getFeatureBits - Return the feature bits.
71 const FeatureBitset& getFeatureBits() const {
75 /// setFeatureBits - Set the feature bits.
77 void setFeatureBits(const FeatureBitset &FeatureBits_) {
78 FeatureBits = FeatureBits_;
82 /// Initialize the scheduling model and feature bits.
84 /// FIXME: Find a way to stick this in the constructor, since it should only
85 /// be called during initialization.
86 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
89 /// Set the features to the default for the given CPU.
90 void setDefaultFeatures(StringRef CPU);
92 /// ToggleFeature - Toggle a feature and returns the re-computed feature
93 /// bits. This version does not change the implied bits.
94 FeatureBitset ToggleFeature(uint64_t FB);
96 /// ToggleFeature - Toggle a feature and returns the re-computed feature
97 /// bits. This version does not change the implied bits.
98 FeatureBitset ToggleFeature(const FeatureBitset& FB);
100 /// ToggleFeature - Toggle a set of features and returns the re-computed
101 /// feature bits. This version will also change all implied bits.
102 FeatureBitset ToggleFeature(StringRef FS);
104 /// Apply a feature flag and return the re-computed feature bits, including
105 /// all feature bits implied by the flag.
106 FeatureBitset ApplyFeatureFlag(StringRef FS);
108 /// getSchedModelForCPU - Get the machine model of a CPU.
110 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
112 /// Get the machine model for this subtarget's CPU.
113 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
115 /// Return an iterator at the first process resource consumed by the given
116 /// scheduling class.
117 const MCWriteProcResEntry *getWriteProcResBegin(
118 const MCSchedClassDesc *SC) const {
119 return &WriteProcResTable[SC->WriteProcResIdx];
121 const MCWriteProcResEntry *getWriteProcResEnd(
122 const MCSchedClassDesc *SC) const {
123 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
126 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
127 unsigned DefIdx) const {
128 assert(DefIdx < SC->NumWriteLatencyEntries &&
129 "MachineModel does not specify a WriteResource for DefIdx");
131 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
134 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
135 unsigned WriteResID) const {
136 // TODO: The number of read advance entries in a class can be significant
137 // (~50). Consider compressing the WriteID into a dense ID of those that are
138 // used by ReadAdvance and representing them as a bitset.
139 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
140 *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
141 if (I->UseIdx < UseIdx)
143 if (I->UseIdx > UseIdx)
145 // Find the first WriteResIdx match, which has the highest cycle count.
146 if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
153 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
155 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
157 /// Initialize an InstrItineraryData instance.
158 void initInstrItins(InstrItineraryData &InstrItins) const;
160 /// Check whether the CPU string is valid.
161 bool isCPUStringValid(StringRef CPU) const {
162 auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
163 [=](const SubtargetFeatureKV &KV) {
164 return CPU == KV.Key;
166 return Found != ProcDesc.end();
170 } // End llvm namespace