1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/MC/SubtargetFeature.h"
25 //===----------------------------------------------------------------------===//
27 /// MCSubtargetInfo - Generic base class for all target subtargets.
29 class MCSubtargetInfo {
30 Triple TargetTriple; // Target triple
31 std::string CPU; // CPU being targeted.
32 ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
33 ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
35 // Scheduler machine model
36 const SubtargetInfoKV *ProcSchedModels;
37 const MCWriteProcResEntry *WriteProcResTable;
38 const MCWriteLatencyEntry *WriteLatencyTable;
39 const MCReadAdvanceEntry *ReadAdvanceTable;
40 const MCSchedModel *CPUSchedModel;
42 const InstrStage *Stages; // Instruction itinerary stages
43 const unsigned *OperandCycles; // Itinerary operand cycles
44 const unsigned *ForwardingPaths; // Forwarding paths
45 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
48 void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
49 ArrayRef<SubtargetFeatureKV> PF,
50 ArrayRef<SubtargetFeatureKV> PD,
51 const SubtargetInfoKV *ProcSched,
52 const MCWriteProcResEntry *WPR,
53 const MCWriteLatencyEntry *WL,
54 const MCReadAdvanceEntry *RA, const InstrStage *IS,
55 const unsigned *OC, const unsigned *FP);
57 /// getTargetTriple - Return the target triple string.
58 const Triple &getTargetTriple() const { return TargetTriple; }
60 /// getCPU - Return the CPU string.
61 StringRef getCPU() const {
65 /// getFeatureBits - Return the feature bits.
67 const FeatureBitset& getFeatureBits() const {
71 /// setFeatureBits - Set the feature bits.
73 void setFeatureBits(const FeatureBitset &FeatureBits_) {
74 FeatureBits = FeatureBits_;
77 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
78 /// feature string). Recompute feature bits and scheduling model.
79 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
81 /// ToggleFeature - Toggle a feature and returns the re-computed feature
82 /// bits. This version does not change the implied bits.
83 FeatureBitset ToggleFeature(uint64_t FB);
85 /// ToggleFeature - Toggle a feature and returns the re-computed feature
86 /// bits. This version does not change the implied bits.
87 FeatureBitset ToggleFeature(const FeatureBitset& FB);
89 /// ToggleFeature - Toggle a set of features and returns the re-computed
90 /// feature bits. This version will also change all implied bits.
91 FeatureBitset ToggleFeature(StringRef FS);
93 /// Apply a feature flag and return the re-computed feature bits, including
94 /// all feature bits implied by the flag.
95 FeatureBitset ApplyFeatureFlag(StringRef FS);
97 /// getSchedModelForCPU - Get the machine model of a CPU.
99 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
101 /// Get the machine model for this subtarget's CPU.
102 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
104 /// Return an iterator at the first process resource consumed by the given
105 /// scheduling class.
106 const MCWriteProcResEntry *getWriteProcResBegin(
107 const MCSchedClassDesc *SC) const {
108 return &WriteProcResTable[SC->WriteProcResIdx];
110 const MCWriteProcResEntry *getWriteProcResEnd(
111 const MCSchedClassDesc *SC) const {
112 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
115 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
116 unsigned DefIdx) const {
117 assert(DefIdx < SC->NumWriteLatencyEntries &&
118 "MachineModel does not specify a WriteResource for DefIdx");
120 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
123 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
124 unsigned WriteResID) const {
125 // TODO: The number of read advance entries in a class can be significant
126 // (~50). Consider compressing the WriteID into a dense ID of those that are
127 // used by ReadAdvance and representing them as a bitset.
128 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
129 *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
130 if (I->UseIdx < UseIdx)
132 if (I->UseIdx > UseIdx)
134 // Find the first WriteResIdx match, which has the highest cycle count.
135 if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
142 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
144 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
146 /// Initialize an InstrItineraryData instance.
147 void initInstrItins(InstrItineraryData &InstrItins) const;
149 /// Check whether the CPU string is valid.
150 bool isCPUStringValid(StringRef CPU) const {
151 auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
152 [=](const SubtargetFeatureKV &KV) {
153 return CPU == KV.Key;
155 return Found != ProcDesc.end();
159 } // End llvm namespace