1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
26 class MachineFunction;
29 /// MRegisterDesc - This record contains all of the information known about a
30 /// particular register. The AliasSet field (if not null) contains a pointer to
31 /// a Zero terminated array of registers that this register aliases. This is
32 /// needed for architectures like X86 which have AL alias AX alias EAX.
33 /// Registers that this does not apply to simply should set this to null.
35 struct MRegisterDesc {
36 const char *Name; // Assembly language name for the register
37 const unsigned *AliasSet; // Register Alias Set, described above
38 unsigned char SpillSize; // Size of this register in bytes
39 unsigned char SpillAlignment; // Alignment of stack slot for this reg
42 class TargetRegisterClass {
44 typedef const unsigned* iterator;
45 typedef const unsigned* const_iterator;
48 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
49 const iterator RegsBegin, RegsEnd;
51 TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
52 : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
53 virtual ~TargetRegisterClass() {} // Allow subclasses
55 // begin/end - Return all of the registers in this class.
56 iterator begin() const { return RegsBegin; }
57 iterator end() const { return RegsEnd; }
59 // getNumRegs - Return the number of registers in this class
60 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
62 // getRegister - Return the specified register in the class
63 unsigned getRegister(unsigned i) const {
64 assert(i < getNumRegs() && "Register number out of range!");
68 /// contains - Return true if the specified register is included in this
70 bool contains(unsigned Reg) const {
71 for (iterator I = begin(), E = end(); I != E; ++I)
72 if (*I == Reg) return true;
76 /// allocation_order_begin/end - These methods define a range of registers
77 /// which specify the registers in this class that are valid to register
78 /// allocate, and the preferred order to allocate them in. For example,
79 /// callee saved registers should be at the end of the list, because it is
80 /// cheaper to allocate caller saved registers.
82 /// These methods take a MachineFunction argument, which can be used to tune
83 /// the allocatable registers based on the characteristics of the function.
84 /// One simple example is that the frame pointer register can be used if
85 /// frame-pointer-elimination is performed.
87 /// By default, these methods return all registers in the class.
89 virtual iterator allocation_order_begin(MachineFunction &MF) const {
92 virtual iterator allocation_order_end(MachineFunction &MF) const {
98 /// getSize - Return the size of the register in bytes, which is also the size
99 /// of a stack slot allocated to hold a spilled copy of this register.
100 unsigned getSize() const { return RegSize; }
102 /// getAlignment - Return the minimum required alignment for a register of
104 unsigned getAlignment() const { return Alignment; }
108 /// MRegisterInfo base class - We assume that the target defines a static array
109 /// of MRegisterDesc objects that represent all of the machine registers that
110 /// the target has. As such, we simply have to track a pointer to this array so
111 /// that we can turn register number into a register descriptor.
113 class MRegisterInfo {
115 typedef const TargetRegisterClass * const * regclass_iterator;
117 const MRegisterDesc *Desc; // Pointer to the descriptor array
118 unsigned NumRegs; // Number of entries in the array
120 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
122 const TargetRegisterClass **PhysRegClasses; // Reg class for each register
123 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
125 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
126 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
127 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
128 virtual ~MRegisterInfo();
131 enum { // Define some target independent constants
132 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
133 /// This is used as the destination register for instructions that do not
134 /// produce a value. Some frontends may use this as an operand register to
135 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
136 /// which always PRODUCES the value 0. The X86 backend does not use this
137 /// value as an operand register, except for memory references.
141 /// FirstVirtualRegister - This is the first register number that is
142 /// considered to be a 'virtual' register, which is part of the SSA
143 /// namespace. This must be the same for all targets, which means that each
144 /// target is limited to 1024 registers.
146 FirstVirtualRegister = 1024,
149 /// isPhysicalRegister - Return true if the specified register number is in
150 /// the physical register namespace.
151 static bool isPhysicalRegister(unsigned Reg) {
152 assert(Reg && "this is not a register!");
153 return Reg < FirstVirtualRegister;
156 /// isVirtualRegister - Return true if the specified register number is in
157 /// the virtual register namespace.
158 static bool isVirtualRegister(unsigned Reg) {
159 assert(Reg && "this is not a register!");
160 return Reg >= FirstVirtualRegister;
163 /// getAllocatableSet - Returns a bitset indexed by register number
164 /// indicating if a register is allocatable or not.
165 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
167 const MRegisterDesc &operator[](unsigned RegNo) const {
168 assert(RegNo < NumRegs &&
169 "Attempting to access record for invalid register number!");
173 /// Provide a get method, equivalent to [], but more useful if we have a
174 /// pointer to this object.
176 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
178 /// getRegClass - Return the register class for the specified physical
181 const TargetRegisterClass *getRegClass(unsigned RegNo) const {
182 assert(RegNo < NumRegs && "Register number out of range!");
183 assert(PhysRegClasses[RegNo] && "Register is not in a class!");
184 return PhysRegClasses[RegNo];
187 /// getAliasSet - Return the set of registers aliased by the specified
188 /// register, or a null list of there are none. The list returned is zero
191 const unsigned *getAliasSet(unsigned RegNo) const {
192 return get(RegNo).AliasSet;
195 /// getName - Return the symbolic target specific name for the specified
196 /// physical register.
197 const char *getName(unsigned RegNo) const {
198 return get(RegNo).Name;
201 /// getSpillSize - Return the size in bits required of a stack slot used to
202 /// spill register into.
203 unsigned getSpillSize(unsigned RegNo) const {
204 return get(RegNo).SpillSize;
207 /// getSpillAlignment - Return the alignment required by a stack slot used to
208 /// spill register into.
209 unsigned getSpillAlignment(unsigned RegNo) const {
210 return get(RegNo).SpillAlignment;
213 /// getNumRegs - Return the number of registers this target has
214 /// (useful for sizing arrays holding per register information)
215 unsigned getNumRegs() const {
219 /// areAliases - Returns true if the two registers alias each other,
221 bool areAliases(unsigned regA, unsigned regB) const {
222 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
223 if (*Alias == regB) return true;
227 virtual const unsigned* getCalleeSaveRegs() const = 0;
230 //===--------------------------------------------------------------------===//
231 // Register Class Information
234 /// Register class iterators
236 regclass_iterator regclass_begin() const { return RegClassBegin; }
237 regclass_iterator regclass_end() const { return RegClassEnd; }
239 unsigned getNumRegClasses() const {
240 return regclass_end()-regclass_begin();
243 //===--------------------------------------------------------------------===//
244 // Interfaces used by the register allocator and stack frame
245 // manipulation passes to move data around between registers,
246 // immediates and memory. The return value is the number of
247 // instructions added to (negative if removed from) the basic block.
250 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
251 MachineBasicBlock::iterator MI,
252 unsigned SrcReg, int FrameIndex) const = 0;
254 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
255 MachineBasicBlock::iterator MI,
256 unsigned DestReg, int FrameIndex) const = 0;
258 virtual void copyRegToReg(MachineBasicBlock &MBB,
259 MachineBasicBlock::iterator MI,
260 unsigned DestReg, unsigned SrcReg,
261 const TargetRegisterClass *RC) const = 0;
264 /// foldMemoryOperand - Attempt to fold a load or store of the
265 /// specified stack slot into the specified machine instruction for
266 /// the specified operand. If this is possible, a new instruction
267 /// is returned with the specified operand folded, otherwise NULL is
268 /// returned. The client is responsible for removing the old
269 /// instruction and adding the new one in the instruction stream
270 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
272 int FrameIndex) const {
276 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
277 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
278 /// targets use pseudo instructions in order to abstract away the difference
279 /// between operating with a frame pointer and operating without, through the
280 /// use of these two instructions.
282 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
283 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
286 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
287 /// code insertion to eliminate call frame setup and destroy pseudo
288 /// instructions (but only if the Target is using them). It is responsible
289 /// for eliminating these instructions, replacing them with concrete
290 /// instructions. This method need only be implemented if using call frame
291 /// setup/destroy pseudo instructions.
294 eliminateCallFramePseudoInstr(MachineFunction &MF,
295 MachineBasicBlock &MBB,
296 MachineBasicBlock::iterator MI) const {
297 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
298 "eliminateCallFramePseudoInstr must be implemented if using"
299 " call frame setup/destroy pseudo instructions!");
300 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
303 /// processFunctionBeforeFrameFinalized - This method is called immediately
304 /// before the specified functions frame layout (MF.getFrameInfo()) is
305 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
306 /// replaced with direct constants. This method is optional. The return value
307 /// is the number of instructions added to (negative if removed from) the
310 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
313 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
314 /// frame indices from instructions which may use them. The instruction
315 /// referenced by the iterator contains an MO_FrameIndex operand which must be
316 /// eliminated by this method. This method may modify or replace the
317 /// specified instruction, as long as it keeps the iterator pointing the the
318 /// finished product. The return value is the number of instructions
319 /// added to (negative if removed from) the basic block.
321 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
323 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
324 /// the function. The return value is the number of instructions
325 /// added to (negative if removed from) the basic block (entry for prologue).
327 virtual void emitPrologue(MachineFunction &MF) const = 0;
328 virtual void emitEpilogue(MachineFunction &MF,
329 MachineBasicBlock &MBB) const = 0;
332 // This is useful when building DenseMaps keyed on virtual registers
333 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
334 unsigned operator()(unsigned Reg) const {
335 return Reg - MRegisterInfo::FirstVirtualRegister;
339 } // End llvm namespace