1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
28 class CalleeSavedInfo;
29 class MachineFunction;
31 class MachineLocation;
37 class TargetRegisterClass;
40 /// TargetRegisterDesc - This record contains all of the information known about
41 /// a particular register. The AliasSet field (if not null) contains a pointer
42 /// to a Zero terminated array of registers that this register aliases. This is
43 /// needed for architectures like X86 which have AL alias AX alias EAX.
44 /// Registers that this does not apply to simply should set this to null.
45 /// The SubRegs field is a zero terminated array of registers that are
46 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
47 /// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
48 /// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
49 /// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
50 /// terminated array of registers that are super-registers of the specific
51 /// register, e.g. RAX, EAX, are super-registers of AX.
53 struct TargetRegisterDesc {
54 const char *Name; // Assembly language name for the register
55 const unsigned *AliasSet; // Register Alias Set, described above
56 const unsigned *SubRegs; // Sub-register set, described above
57 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
58 const unsigned *SuperRegs; // Super-register set, described above
61 class TargetRegisterClass {
63 typedef const unsigned* iterator;
64 typedef const unsigned* const_iterator;
66 typedef const MVT::ValueType* vt_iterator;
67 typedef const TargetRegisterClass* const * sc_iterator;
71 const vt_iterator VTs;
72 const sc_iterator SubClasses;
73 const sc_iterator SuperClasses;
74 const sc_iterator SubRegClasses;
75 const sc_iterator SuperRegClasses;
76 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
78 const iterator RegsBegin, RegsEnd;
80 TargetRegisterClass(unsigned id,
81 const MVT::ValueType *vts,
82 const TargetRegisterClass * const *subcs,
83 const TargetRegisterClass * const *supcs,
84 const TargetRegisterClass * const *subregcs,
85 const TargetRegisterClass * const *superregcs,
86 unsigned RS, unsigned Al, int CC,
87 iterator RB, iterator RE)
88 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
89 SubRegClasses(subregcs), SuperRegClasses(superregcs),
90 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
91 virtual ~TargetRegisterClass() {} // Allow subclasses
93 /// getID() - Return the register class ID number.
95 unsigned getID() const { return ID; }
97 /// begin/end - Return all of the registers in this class.
99 iterator begin() const { return RegsBegin; }
100 iterator end() const { return RegsEnd; }
102 /// getNumRegs - Return the number of registers in this class.
104 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
106 /// getRegister - Return the specified register in the class.
108 unsigned getRegister(unsigned i) const {
109 assert(i < getNumRegs() && "Register number out of range!");
113 /// contains - Return true if the specified register is included in this
115 bool contains(unsigned Reg) const {
116 for (iterator I = begin(), E = end(); I != E; ++I)
117 if (*I == Reg) return true;
121 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
123 bool hasType(MVT::ValueType vt) const {
124 for(int i = 0; VTs[i] != MVT::Other; ++i)
130 /// vt_begin / vt_end - Loop over all of the value types that can be
131 /// represented by values in this register class.
132 vt_iterator vt_begin() const {
136 vt_iterator vt_end() const {
138 while (*I != MVT::Other) ++I;
142 /// hasSubClass - return true if the specified TargetRegisterClass is a
143 /// sub-register class of this TargetRegisterClass.
144 bool hasSubClass(const TargetRegisterClass *cs) const {
145 for (int i = 0; SubClasses[i] != NULL; ++i)
146 if (SubClasses[i] == cs)
151 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
152 /// this register class.
153 sc_iterator subclasses_begin() const {
157 sc_iterator subclasses_end() const {
158 sc_iterator I = SubClasses;
159 while (*I != NULL) ++I;
163 /// hasSuperClass - return true if the specified TargetRegisterClass is a
164 /// super-register class of this TargetRegisterClass.
165 bool hasSuperClass(const TargetRegisterClass *cs) const {
166 for (int i = 0; SuperClasses[i] != NULL; ++i)
167 if (SuperClasses[i] == cs)
172 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
173 /// of this register class.
174 sc_iterator superclasses_begin() const {
178 sc_iterator superclasses_end() const {
179 sc_iterator I = SuperClasses;
180 while (*I != NULL) ++I;
184 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
185 /// class of a sub-register class for this TargetRegisterClass.
186 bool hasSubRegClass(const TargetRegisterClass *cs) const {
187 for (int i = 0; SubRegClasses[i] != NULL; ++i)
188 if (SubRegClasses[i] == cs)
193 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
194 /// class of a sub-register class for this TargetRegisterClass.
195 bool hasClassForSubReg(unsigned SubReg) const {
197 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
203 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
204 /// at idx for this TargetRegisterClass.
205 sc_iterator getClassForSubReg(unsigned SubReg) const {
207 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
209 return &SubRegClasses[i];
210 assert(0 && "Invalid subregister index for register class");
214 /// subregclasses_begin / subregclasses_end - Loop over all of
215 /// the subregister classes of this register class.
216 sc_iterator subregclasses_begin() const {
217 return SubRegClasses;
220 sc_iterator subregclasses_end() const {
221 sc_iterator I = SubRegClasses;
222 while (*I != NULL) ++I;
226 /// superregclasses_begin / superregclasses_end - Loop over all of
227 /// the superregister classes of this register class.
228 sc_iterator superregclasses_begin() const {
229 return SuperRegClasses;
232 sc_iterator superregclasses_end() const {
233 sc_iterator I = SuperRegClasses;
234 while (*I != NULL) ++I;
238 /// allocation_order_begin/end - These methods define a range of registers
239 /// which specify the registers in this class that are valid to register
240 /// allocate, and the preferred order to allocate them in. For example,
241 /// callee saved registers should be at the end of the list, because it is
242 /// cheaper to allocate caller saved registers.
244 /// These methods take a MachineFunction argument, which can be used to tune
245 /// the allocatable registers based on the characteristics of the function.
246 /// One simple example is that the frame pointer register can be used if
247 /// frame-pointer-elimination is performed.
249 /// By default, these methods return all registers in the class.
251 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
254 virtual iterator allocation_order_end(const MachineFunction &MF) const {
260 /// getSize - Return the size of the register in bytes, which is also the size
261 /// of a stack slot allocated to hold a spilled copy of this register.
262 unsigned getSize() const { return RegSize; }
264 /// getAlignment - Return the minimum required alignment for a register of
266 unsigned getAlignment() const { return Alignment; }
268 /// getCopyCost - Return the cost of copying a value between two registers in
270 int getCopyCost() const { return CopyCost; }
274 /// MRegisterInfo base class - We assume that the target defines a static array
275 /// of TargetRegisterDesc objects that represent all of the machine registers
276 /// that the target has. As such, we simply have to track a pointer to this
277 /// array so that we can turn register number into a register descriptor.
279 class MRegisterInfo {
281 typedef const TargetRegisterClass * const * regclass_iterator;
283 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
284 unsigned NumRegs; // Number of entries in the array
286 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
288 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
290 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
291 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
292 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
293 virtual ~MRegisterInfo();
296 enum { // Define some target independent constants
297 /// NoRegister - This physical register is not a real target register. It
298 /// is useful as a sentinal.
301 /// FirstVirtualRegister - This is the first register number that is
302 /// considered to be a 'virtual' register, which is part of the SSA
303 /// namespace. This must be the same for all targets, which means that each
304 /// target is limited to 1024 registers.
305 FirstVirtualRegister = 1024
308 /// isPhysicalRegister - Return true if the specified register number is in
309 /// the physical register namespace.
310 static bool isPhysicalRegister(unsigned Reg) {
311 assert(Reg && "this is not a register!");
312 return Reg < FirstVirtualRegister;
315 /// isVirtualRegister - Return true if the specified register number is in
316 /// the virtual register namespace.
317 static bool isVirtualRegister(unsigned Reg) {
318 assert(Reg && "this is not a register!");
319 return Reg >= FirstVirtualRegister;
322 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
323 /// register of the given type.
324 const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
327 /// getAllocatableSet - Returns a bitset indexed by register number
328 /// indicating if a register is allocatable or not. If a register class is
329 /// specified, returns the subset for the class.
330 BitVector getAllocatableSet(MachineFunction &MF,
331 const TargetRegisterClass *RC = NULL) const;
333 const TargetRegisterDesc &operator[](unsigned RegNo) const {
334 assert(RegNo < NumRegs &&
335 "Attempting to access record for invalid register number!");
339 /// Provide a get method, equivalent to [], but more useful if we have a
340 /// pointer to this object.
342 const TargetRegisterDesc &get(unsigned RegNo) const {
343 return operator[](RegNo);
346 /// getAliasSet - Return the set of registers aliased by the specified
347 /// register, or a null list of there are none. The list returned is zero
350 const unsigned *getAliasSet(unsigned RegNo) const {
351 return get(RegNo).AliasSet;
354 /// getSubRegisters - Return the set of registers that are sub-registers of
355 /// the specified register, or a null list of there are none. The list
356 /// returned is zero terminated.
358 const unsigned *getSubRegisters(unsigned RegNo) const {
359 return get(RegNo).SubRegs;
362 /// getImmediateSubRegisters - Return the set of registers that are immediate
363 /// sub-registers of the specified register, or a null list of there are none.
364 /// The list returned is zero terminated.
366 const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
367 return get(RegNo).ImmSubRegs;
370 /// getSuperRegisters - Return the set of registers that are super-registers
371 /// of the specified register, or a null list of there are none. The list
372 /// returned is zero terminated.
374 const unsigned *getSuperRegisters(unsigned RegNo) const {
375 return get(RegNo).SuperRegs;
378 /// getName - Return the symbolic target specific name for the specified
379 /// physical register.
380 const char *getName(unsigned RegNo) const {
381 return get(RegNo).Name;
384 /// getNumRegs - Return the number of registers this target has (useful for
385 /// sizing arrays holding per register information)
386 unsigned getNumRegs() const {
390 /// areAliases - Returns true if the two registers alias each other, false
392 bool areAliases(unsigned regA, unsigned regB) const {
393 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
394 if (*Alias == regB) return true;
398 /// regsOverlap - Returns true if the two registers are equal or alias each
399 /// other. The registers may be virtual register.
400 bool regsOverlap(unsigned regA, unsigned regB) const {
404 if (isVirtualRegister(regA) || isVirtualRegister(regB))
406 return areAliases(regA, regB);
409 /// isSubRegister - Returns true if regB is a sub-register of regA.
411 bool isSubRegister(unsigned regA, unsigned regB) const {
412 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
413 if (*SR == regB) return true;
417 /// isSuperRegister - Returns true if regB is a super-register of regA.
419 bool isSuperRegister(unsigned regA, unsigned regB) const {
420 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
421 if (*SR == regB) return true;
425 /// getCalleeSavedRegs - Return a null-terminated list of all of the
426 /// callee saved registers on this target. The register should be in the
427 /// order of desired callee-save stack frame offset. The first register is
428 /// closed to the incoming stack pointer if stack grows down, and vice versa.
429 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
432 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
433 /// register classes to spill each callee saved register with. The order and
434 /// length of this list match the getCalleeSaveRegs() list.
435 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
436 const MachineFunction *MF) const =0;
438 /// getReservedRegs - Returns a bitset indexed by physical register number
439 /// indicating if a register is a special register that has particular uses
440 /// and should be considered unavailable at all times, e.g. SP, RA. This is
441 /// used by register scavenger to determine what registers are free.
442 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
444 /// getSubReg - Returns the physical register number of sub-register "Index"
445 /// for physical register RegNo.
446 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
448 //===--------------------------------------------------------------------===//
449 // Register Class Information
452 /// Register class iterators
454 regclass_iterator regclass_begin() const { return RegClassBegin; }
455 regclass_iterator regclass_end() const { return RegClassEnd; }
457 unsigned getNumRegClasses() const {
458 return regclass_end()-regclass_begin();
461 /// getRegClass - Returns the register class associated with the enumeration
462 /// value. See class TargetOperandInfo.
463 const TargetRegisterClass *getRegClass(unsigned i) const {
464 assert(i <= getNumRegClasses() && "Register Class ID out of range");
465 return i ? RegClassBegin[i - 1] : NULL;
468 //===--------------------------------------------------------------------===//
469 // Interfaces used by the register allocator and stack frame
470 // manipulation passes to move data around between registers,
471 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
474 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
475 /// saved registers and returns true if it isn't possible / profitable to do
476 /// so by issuing a series of store instructions via
477 /// storeRegToStackSlot(). Returns false otherwise.
478 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
479 MachineBasicBlock::iterator MI,
480 const std::vector<CalleeSavedInfo> &CSI) const {
484 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
485 /// saved registers and returns true if it isn't possible / profitable to do
486 /// so by issuing a series of load instructions via loadRegToStackSlot().
487 /// Returns false otherwise.
488 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
489 MachineBasicBlock::iterator MI,
490 const std::vector<CalleeSavedInfo> &CSI) const {
494 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
495 MachineBasicBlock::iterator MI,
496 unsigned SrcReg, bool isKill, int FrameIndex,
497 const TargetRegisterClass *RC) const = 0;
499 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
500 SmallVectorImpl<MachineOperand> &Addr,
501 const TargetRegisterClass *RC,
502 SmallVectorImpl<MachineInstr*> &NewMIs) const = 0;
504 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
505 MachineBasicBlock::iterator MI,
506 unsigned DestReg, int FrameIndex,
507 const TargetRegisterClass *RC) const = 0;
509 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
510 SmallVectorImpl<MachineOperand> &Addr,
511 const TargetRegisterClass *RC,
512 SmallVectorImpl<MachineInstr*> &NewMIs) const =0;
514 virtual void copyRegToReg(MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator MI,
516 unsigned DestReg, unsigned SrcReg,
517 const TargetRegisterClass *DestRC,
518 const TargetRegisterClass *SrcRC) const = 0;
520 /// getCrossCopyRegClass - Returns a legal register class to copy a register
521 /// in the specified class to or from. Returns NULL if it is possible to copy
522 /// between a two registers of the specified class.
523 virtual const TargetRegisterClass *
524 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
528 /// reMaterialize - Re-issue the specified 'original' instruction at the
529 /// specific location targeting a new destination register.
530 virtual void reMaterialize(MachineBasicBlock &MBB,
531 MachineBasicBlock::iterator MI,
533 const MachineInstr *Orig) const = 0;
535 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
536 /// slot into the specified machine instruction for the specified operand(s).
537 /// If this is possible, a new instruction is returned with the specified
538 /// operand folded, otherwise NULL is returned. The client is responsible for
539 /// removing the old instruction and adding the new one in the instruction
541 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
542 SmallVectorImpl<unsigned> &Ops,
543 int FrameIndex) const {
547 /// foldMemoryOperand - Same as the previous version except it allows folding
548 /// of any load and store from / to any address, not just from a specific
550 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
551 SmallVectorImpl<unsigned> &Ops,
552 MachineInstr* LoadMI) const {
556 /// canFoldMemoryOperand - Returns true if the specified load / store is
557 /// folding is possible.
559 bool canFoldMemoryOperand(MachineInstr *MI,
560 SmallVectorImpl<unsigned> &Ops) const{
564 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
565 /// a a store or a load and a store into two or more instruction. If this is
566 /// possible, returns true as well as the new instructions by reference.
567 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
568 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
569 SmallVectorImpl<MachineInstr*> &NewMIs) const{
573 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
574 SmallVectorImpl<SDNode*> &NewNodes) const {
578 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
579 /// instruction after load / store are unfolded from an instruction of the
580 /// specified opcode. It returns zero if the specified unfolding is not
582 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
583 bool UnfoldLoad, bool UnfoldStore) const {
587 /// targetHandlesStackFrameRounding - Returns true if the target is
588 /// responsible for rounding up the stack frame (probably at emitPrologue
590 virtual bool targetHandlesStackFrameRounding() const {
594 /// requiresRegisterScavenging - returns true if the target requires (and can
595 /// make use of) the register scavenger.
596 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
600 /// hasFP - Return true if the specified function should have a dedicated
601 /// frame pointer register. For most targets this is true only if the function
602 /// has variable sized allocas or if frame pointer elimination is disabled.
603 virtual bool hasFP(const MachineFunction &MF) const = 0;
605 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
606 // not required, we reserve argument space for call sites in the function
607 // immediately on entry to the current function. This eliminates the need for
608 // add/sub sp brackets around call sites. Returns true if the call frame is
609 // included as part of the stack frame.
610 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
614 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
615 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
616 /// targets use pseudo instructions in order to abstract away the difference
617 /// between operating with a frame pointer and operating without, through the
618 /// use of these two instructions.
620 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
621 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
624 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
625 /// code insertion to eliminate call frame setup and destroy pseudo
626 /// instructions (but only if the Target is using them). It is responsible
627 /// for eliminating these instructions, replacing them with concrete
628 /// instructions. This method need only be implemented if using call frame
629 /// setup/destroy pseudo instructions.
632 eliminateCallFramePseudoInstr(MachineFunction &MF,
633 MachineBasicBlock &MBB,
634 MachineBasicBlock::iterator MI) const {
635 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
636 "eliminateCallFramePseudoInstr must be implemented if using"
637 " call frame setup/destroy pseudo instructions!");
638 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
641 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
642 /// before PrologEpilogInserter scans the physical registers used to determine
643 /// what callee saved registers should be spilled. This method is optional.
644 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
645 RegScavenger *RS = NULL) const {
649 /// processFunctionBeforeFrameFinalized - This method is called immediately
650 /// before the specified functions frame layout (MF.getFrameInfo()) is
651 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
652 /// replaced with direct constants. This method is optional.
654 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
657 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
658 /// frame indices from instructions which may use them. The instruction
659 /// referenced by the iterator contains an MO_FrameIndex operand which must be
660 /// eliminated by this method. This method may modify or replace the
661 /// specified instruction, as long as it keeps the iterator pointing the the
662 /// finished product. SPAdj is the SP adjustment due to call frame setup
663 /// instruction. The return value is the number of instructions added to
664 /// (negative if removed from) the basic block.
666 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
667 int SPAdj, RegScavenger *RS=NULL) const = 0;
669 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
670 /// the function. The return value is the number of instructions
671 /// added to (negative if removed from) the basic block (entry for prologue).
673 virtual void emitPrologue(MachineFunction &MF) const = 0;
674 virtual void emitEpilogue(MachineFunction &MF,
675 MachineBasicBlock &MBB) const = 0;
677 //===--------------------------------------------------------------------===//
678 /// Debug information queries.
680 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
681 /// number. Returns -1 if there is no equivalent value. The second
682 /// parameter allows targets to use different numberings for EH info and
684 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
686 /// getFrameRegister - This method should return the register used as a base
687 /// for values allocated in the current stack frame.
688 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
690 /// getRARegister - This method should return the register where the return
691 /// address can be found.
692 virtual unsigned getRARegister() const = 0;
694 /// getLocation - This method should return the actual location of a frame
695 /// variable given the frame index. The location is returned in ML.
696 /// Subclasses should override this method for special handling of frame
697 /// variables and call MRegisterInfo::getLocation for the default action.
698 virtual void getLocation(MachineFunction &MF, unsigned Index,
699 MachineLocation &ML) const;
701 /// getInitialFrameState - Returns a list of machine moves that are assumed
702 /// on entry to all functions. Note that LabelID is ignored (assumed to be
703 /// the beginning of the function.)
704 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
707 // This is useful when building IndexedMaps keyed on virtual registers
708 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
709 unsigned operator()(unsigned Reg) const {
710 return Reg - MRegisterInfo::FirstVirtualRegister;
714 } // End llvm namespace