1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
20 #include "llvm/CodeGen/MachineBasicBlock.h"
25 class MachineFunction;
28 /// MRegisterDesc - This record contains all of the information known about a
29 /// particular register. The AliasSet field (if not null) contains a pointer to
30 /// a Zero terminated array of registers that this register aliases. This is
31 /// needed for architectures like X86 which have AL alias AX alias EAX.
32 /// Registers that this does not apply to simply should set this to null.
34 struct MRegisterDesc {
35 const char *Name; // Assembly language name for the register
36 const unsigned *AliasSet; // Register Alias Set, described above
37 unsigned Flags; // Flags identifying register properties (below)
38 unsigned TSFlags; // Target Specific Flags
41 class TargetRegisterClass {
43 typedef const unsigned* iterator;
44 typedef const unsigned* const_iterator;
47 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
48 const iterator RegsBegin, RegsEnd;
50 TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
51 : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
52 virtual ~TargetRegisterClass() {} // Allow subclasses
54 // begin/end - Return all of the registers in this class.
55 iterator begin() const { return RegsBegin; }
56 iterator end() const { return RegsEnd; }
58 // getNumRegs - Return the number of registers in this class
59 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
61 // getRegister - Return the specified register in the class
62 unsigned getRegister(unsigned i) const {
63 assert(i < getNumRegs() && "Register number out of range!");
67 /// allocation_order_begin/end - These methods define a range of registers
68 /// which specify the registers in this class that are valid to register
69 /// allocate, and the preferred order to allocate them in. For example,
70 /// callee saved registers should be at the end of the list, because it is
71 /// cheaper to allocate caller saved registers.
73 /// These methods take a MachineFunction argument, which can be used to tune
74 /// the allocatable registers based on the characteristics of the function.
75 /// One simple example is that the frame pointer register can be used if
76 /// frame-pointer-elimination is performed.
78 /// By default, these methods return all registers in the class.
80 virtual iterator allocation_order_begin(MachineFunction &MF) const {
83 virtual iterator allocation_order_end(MachineFunction &MF) const {
89 /// getSize - Return the size of the register in bytes, which is also the size
90 /// of a stack slot allocated to hold a spilled copy of this register.
91 unsigned getSize() const { return RegSize; }
93 /// getAlignment - Return the minimum required alignment for a register of
95 unsigned getAlignment() const { return Alignment; }
99 /// MRegisterInfo base class - We assume that the target defines a static array
100 /// of MRegisterDesc objects that represent all of the machine registers that
101 /// the target has. As such, we simply have to track a pointer to this array so
102 /// that we can turn register number into a register descriptor.
104 class MRegisterInfo {
106 typedef const TargetRegisterClass * const * regclass_iterator;
108 const MRegisterDesc *Desc; // Pointer to the descriptor array
109 unsigned NumRegs; // Number of entries in the array
111 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
113 const TargetRegisterClass **PhysRegClasses; // Reg class for each register
114 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
116 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
117 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
118 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
119 virtual ~MRegisterInfo();
122 enum { // Define some target independent constants
123 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
124 /// This is used as the destination register for instructions that do not
125 /// produce a value. Some frontends may use this as an operand register to
126 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
127 /// which always PRODUCES the value 0. The X86 backend does not use this
128 /// value as an operand register, except for memory references.
132 /// FirstVirtualRegister - This is the first register number that is
133 /// considered to be a 'virtual' register, which is part of the SSA
134 /// namespace. This must be the same for all targets, which means that each
135 /// target is limited to 1024 registers.
137 FirstVirtualRegister = 1024,
140 /// isPhysicalRegister - Return true if the specified register number is in
141 /// the physical register namespace.
142 static bool isPhysicalRegister(unsigned Reg) {
143 return Reg < FirstVirtualRegister;
146 /// isVirtualRegister - Return true if the specified register number is in
147 /// the virtual register namespace.
148 static bool isVirtualRegister(unsigned Reg) {
149 return Reg >= FirstVirtualRegister;
152 const MRegisterDesc &operator[](unsigned RegNo) const {
153 assert(RegNo < NumRegs &&
154 "Attempting to access record for invalid register number!");
158 /// Provide a get method, equivalent to [], but more useful if we have a
159 /// pointer to this object.
161 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
163 /// getRegClass - Return the register class for the specified physical
166 const TargetRegisterClass *getRegClass(unsigned RegNo) const {
167 assert(RegNo < NumRegs && "Register number out of range!");
168 assert(PhysRegClasses[RegNo] && "Register is not in a class!");
169 return PhysRegClasses[RegNo];
172 /// getAliasSet - Return the set of registers aliased by the specified
173 /// register, or a null list of there are none. The list returned is zero
176 const unsigned *getAliasSet(unsigned RegNo) const {
177 return get(RegNo).AliasSet;
180 /// getName - Return the symbolic target specific name for the specified
181 /// physical register.
182 const char *getName(unsigned RegNo) const {
183 return get(RegNo).Name;
186 /// getNumRegs - Return the number of registers this target has
187 /// (useful for sizing arrays holding per register information)
188 unsigned getNumRegs() const {
192 virtual const unsigned* getCalleeSaveRegs() const = 0;
195 //===--------------------------------------------------------------------===//
196 // Register Class Information
199 /// Register class iterators
201 regclass_iterator regclass_begin() const { return RegClassBegin; }
202 regclass_iterator regclass_end() const { return RegClassEnd; }
204 unsigned getNumRegClasses() const {
205 return regclass_end()-regclass_begin();
208 //===--------------------------------------------------------------------===//
209 // All basic block modifier functions below return the number of
210 // instructions added to (negative if removed from) the basic block
211 // passed as their first argument.
213 // FIXME: This is only needed because we use a std::vector instead
214 // of an ilist to keep MachineBasicBlock instructions. Inserting an
215 // instruction to a MachineBasicBlock invalidates all iterators to
216 // the basic block. The return value can be used to update an index
217 // to the machine basic block instruction vector and circumvent the
218 // iterator elimination problem but this is really not needed if we
219 // move to a better representation.
222 //===--------------------------------------------------------------------===//
223 // Interfaces used by the register allocator and stack frame
224 // manipulation passes to move data around between registers,
225 // immediates and memory. The return value is the number of
226 // instructions added to (negative if removed from) the basic block.
229 virtual int storeRegToStackSlot(MachineBasicBlock &MBB,
230 MachineBasicBlock::iterator MI,
231 unsigned SrcReg, int FrameIndex,
232 const TargetRegisterClass *RC) const = 0;
234 virtual int loadRegFromStackSlot(MachineBasicBlock &MBB,
235 MachineBasicBlock::iterator MI,
236 unsigned DestReg, int FrameIndex,
237 const TargetRegisterClass *RC) const = 0;
239 virtual int copyRegToReg(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator MI,
241 unsigned DestReg, unsigned SrcReg,
242 const TargetRegisterClass *RC) const = 0;
245 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
246 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
247 /// targets use pseudo instructions in order to abstract away the difference
248 /// between operating with a frame pointer and operating without, through the
249 /// use of these two instructions.
251 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
252 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
255 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
256 /// code insertion to eliminate call frame setup and destroy pseudo
257 /// instructions (but only if the Target is using them). It is responsible
258 /// for eliminating these instructions, replacing them with concrete
259 /// instructions. This method need only be implemented if using call frame
260 /// setup/destroy pseudo instructions. The return value is the number of
261 /// instructions added to (negative if removed from) the basic block.
264 eliminateCallFramePseudoInstr(MachineFunction &MF,
265 MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator MI) const {
267 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
268 "eliminateCallFramePseudoInstr must be implemented if using"
269 " call frame setup/destroy pseudo instructions!");
270 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
273 /// processFunctionBeforeFrameFinalized - This method is called immediately
274 /// before the specified functions frame layout (MF.getFrameInfo()) is
275 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
276 /// replaced with direct constants. This method is optional. The return value
277 /// is the number of instructions added to (negative if removed from) the
280 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
283 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
284 /// frame indices from instructions which may use them. The instruction
285 /// referenced by the iterator contains an MO_FrameIndex operand which must be
286 /// eliminated by this method. This method may modify or replace the
287 /// specified instruction, as long as it keeps the iterator pointing the the
288 /// finished product. The return value is the number of instructions
289 /// added to (negative if removed from) the basic block.
291 virtual void eliminateFrameIndex(MachineFunction &MF,
292 MachineBasicBlock::iterator MI) const = 0;
294 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
295 /// the function. The return value is the number of instructions
296 /// added to (negative if removed from) the basic block (entry for prologue).
298 virtual void emitPrologue(MachineFunction &MF) const = 0;
299 virtual void emitEpilogue(MachineFunction &MF,
300 MachineBasicBlock &MBB) const = 0;
303 } // End llvm namespace