1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
28 class MachineFunction;
30 class MachineLocation;
35 class TargetRegisterClass;
38 /// TargetRegisterDesc - This record contains all of the information known about
39 /// a particular register. The AliasSet field (if not null) contains a pointer
40 /// to a Zero terminated array of registers that this register aliases. This is
41 /// needed for architectures like X86 which have AL alias AX alias EAX.
42 /// Registers that this does not apply to simply should set this to null.
43 /// The SubRegs field is a zero terminated array of registers that are
44 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
45 /// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
46 /// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
47 /// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
48 /// terminated array of registers that are super-registers of the specific
49 /// register, e.g. RAX, EAX, are super-registers of AX.
51 struct TargetRegisterDesc {
52 const char *Name; // Assembly language name for the register
53 const unsigned *AliasSet; // Register Alias Set, described above
54 const unsigned *SubRegs; // Sub-register set, described above
55 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
56 const unsigned *SuperRegs; // Super-register set, described above
59 class TargetRegisterClass {
61 typedef const unsigned* iterator;
62 typedef const unsigned* const_iterator;
64 typedef const MVT::ValueType* vt_iterator;
65 typedef const TargetRegisterClass* const * sc_iterator;
69 const vt_iterator VTs;
70 const sc_iterator SubClasses;
71 const sc_iterator SuperClasses;
72 const sc_iterator SubRegClasses;
73 const sc_iterator SuperRegClasses;
74 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
76 const iterator RegsBegin, RegsEnd;
78 TargetRegisterClass(unsigned id,
79 const MVT::ValueType *vts,
80 const TargetRegisterClass * const *subcs,
81 const TargetRegisterClass * const *supcs,
82 const TargetRegisterClass * const *subregcs,
83 const TargetRegisterClass * const *superregcs,
84 unsigned RS, unsigned Al, int CC,
85 iterator RB, iterator RE)
86 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
87 SubRegClasses(subregcs), SuperRegClasses(superregcs),
88 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
89 virtual ~TargetRegisterClass() {} // Allow subclasses
91 /// getID() - Return the register class ID number.
93 unsigned getID() const { return ID; }
95 /// begin/end - Return all of the registers in this class.
97 iterator begin() const { return RegsBegin; }
98 iterator end() const { return RegsEnd; }
100 /// getNumRegs - Return the number of registers in this class.
102 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
104 /// getRegister - Return the specified register in the class.
106 unsigned getRegister(unsigned i) const {
107 assert(i < getNumRegs() && "Register number out of range!");
111 /// contains - Return true if the specified register is included in this
113 bool contains(unsigned Reg) const {
114 for (iterator I = begin(), E = end(); I != E; ++I)
115 if (*I == Reg) return true;
119 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
121 bool hasType(MVT::ValueType vt) const {
122 for(int i = 0; VTs[i] != MVT::Other; ++i)
128 /// vt_begin / vt_end - Loop over all of the value types that can be
129 /// represented by values in this register class.
130 vt_iterator vt_begin() const {
134 vt_iterator vt_end() const {
136 while (*I != MVT::Other) ++I;
140 /// hasSubClass - return true if the specified TargetRegisterClass is a
141 /// sub-register class of this TargetRegisterClass.
142 bool hasSubClass(const TargetRegisterClass *cs) const {
143 for (int i = 0; SubClasses[i] != NULL; ++i)
144 if (SubClasses[i] == cs)
149 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
150 /// this register class.
151 sc_iterator subclasses_begin() const {
155 sc_iterator subclasses_end() const {
156 sc_iterator I = SubClasses;
157 while (*I != NULL) ++I;
161 /// hasSuperClass - return true if the specified TargetRegisterClass is a
162 /// super-register class of this TargetRegisterClass.
163 bool hasSuperClass(const TargetRegisterClass *cs) const {
164 for (int i = 0; SuperClasses[i] != NULL; ++i)
165 if (SuperClasses[i] == cs)
170 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
171 /// of this register class.
172 sc_iterator superclasses_begin() const {
176 sc_iterator superclasses_end() const {
177 sc_iterator I = SuperClasses;
178 while (*I != NULL) ++I;
182 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
183 /// class of a sub-register class for this TargetRegisterClass.
184 bool hasSubRegClass(const TargetRegisterClass *cs) const {
185 for (int i = 0; SubRegClasses[i] != NULL; ++i)
186 if (SubRegClasses[i] == cs)
191 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
192 /// class of a sub-register class for this TargetRegisterClass.
193 bool hasClassForSubReg(unsigned SubReg) const {
195 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
201 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
202 /// at idx for this TargetRegisterClass.
203 sc_iterator getClassForSubReg(unsigned SubReg) const {
205 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
207 return &SubRegClasses[i];
208 assert(0 && "Invalid subregister index for register class");
212 /// subregclasses_begin / subregclasses_end - Loop over all of
213 /// the subregister classes of this register class.
214 sc_iterator subregclasses_begin() const {
215 return SubRegClasses;
218 sc_iterator subregclasses_end() const {
219 sc_iterator I = SubRegClasses;
220 while (*I != NULL) ++I;
224 /// superregclasses_begin / superregclasses_end - Loop over all of
225 /// the superregister classes of this register class.
226 sc_iterator superregclasses_begin() const {
227 return SuperRegClasses;
230 sc_iterator superregclasses_end() const {
231 sc_iterator I = SuperRegClasses;
232 while (*I != NULL) ++I;
236 /// allocation_order_begin/end - These methods define a range of registers
237 /// which specify the registers in this class that are valid to register
238 /// allocate, and the preferred order to allocate them in. For example,
239 /// callee saved registers should be at the end of the list, because it is
240 /// cheaper to allocate caller saved registers.
242 /// These methods take a MachineFunction argument, which can be used to tune
243 /// the allocatable registers based on the characteristics of the function.
244 /// One simple example is that the frame pointer register can be used if
245 /// frame-pointer-elimination is performed.
247 /// By default, these methods return all registers in the class.
249 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
252 virtual iterator allocation_order_end(const MachineFunction &MF) const {
258 /// getSize - Return the size of the register in bytes, which is also the size
259 /// of a stack slot allocated to hold a spilled copy of this register.
260 unsigned getSize() const { return RegSize; }
262 /// getAlignment - Return the minimum required alignment for a register of
264 unsigned getAlignment() const { return Alignment; }
266 /// getCopyCost - Return the cost of copying a value between two registers in
268 int getCopyCost() const { return CopyCost; }
272 /// MRegisterInfo base class - We assume that the target defines a static array
273 /// of TargetRegisterDesc objects that represent all of the machine registers
274 /// that the target has. As such, we simply have to track a pointer to this
275 /// array so that we can turn register number into a register descriptor.
277 class MRegisterInfo {
279 typedef const TargetRegisterClass * const * regclass_iterator;
281 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
282 unsigned NumRegs; // Number of entries in the array
284 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
286 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
288 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
289 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
290 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
291 virtual ~MRegisterInfo();
294 enum { // Define some target independent constants
295 /// NoRegister - This physical register is not a real target register. It
296 /// is useful as a sentinal.
299 /// FirstVirtualRegister - This is the first register number that is
300 /// considered to be a 'virtual' register, which is part of the SSA
301 /// namespace. This must be the same for all targets, which means that each
302 /// target is limited to 1024 registers.
303 FirstVirtualRegister = 1024
306 /// isPhysicalRegister - Return true if the specified register number is in
307 /// the physical register namespace.
308 static bool isPhysicalRegister(unsigned Reg) {
309 assert(Reg && "this is not a register!");
310 return Reg < FirstVirtualRegister;
313 /// isVirtualRegister - Return true if the specified register number is in
314 /// the virtual register namespace.
315 static bool isVirtualRegister(unsigned Reg) {
316 assert(Reg && "this is not a register!");
317 return Reg >= FirstVirtualRegister;
320 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
321 /// register of the given type.
322 const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
325 /// getAllocatableSet - Returns a bitset indexed by register number
326 /// indicating if a register is allocatable or not. If a register class is
327 /// specified, returns the subset for the class.
328 BitVector getAllocatableSet(MachineFunction &MF,
329 const TargetRegisterClass *RC = NULL) const;
331 const TargetRegisterDesc &operator[](unsigned RegNo) const {
332 assert(RegNo < NumRegs &&
333 "Attempting to access record for invalid register number!");
337 /// Provide a get method, equivalent to [], but more useful if we have a
338 /// pointer to this object.
340 const TargetRegisterDesc &get(unsigned RegNo) const {
341 return operator[](RegNo);
344 /// getAliasSet - Return the set of registers aliased by the specified
345 /// register, or a null list of there are none. The list returned is zero
348 const unsigned *getAliasSet(unsigned RegNo) const {
349 return get(RegNo).AliasSet;
352 /// getSubRegisters - Return the set of registers that are sub-registers of
353 /// the specified register, or a null list of there are none. The list
354 /// returned is zero terminated.
356 const unsigned *getSubRegisters(unsigned RegNo) const {
357 return get(RegNo).SubRegs;
360 /// getImmediateSubRegisters - Return the set of registers that are immediate
361 /// sub-registers of the specified register, or a null list of there are none.
362 /// The list returned is zero terminated.
364 const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
365 return get(RegNo).ImmSubRegs;
368 /// getSuperRegisters - Return the set of registers that are super-registers
369 /// of the specified register, or a null list of there are none. The list
370 /// returned is zero terminated.
372 const unsigned *getSuperRegisters(unsigned RegNo) const {
373 return get(RegNo).SuperRegs;
376 /// getName - Return the symbolic target specific name for the specified
377 /// physical register.
378 const char *getName(unsigned RegNo) const {
379 return get(RegNo).Name;
382 /// getNumRegs - Return the number of registers this target has (useful for
383 /// sizing arrays holding per register information)
384 unsigned getNumRegs() const {
388 /// areAliases - Returns true if the two registers alias each other, false
390 bool areAliases(unsigned regA, unsigned regB) const {
391 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
392 if (*Alias == regB) return true;
396 /// regsOverlap - Returns true if the two registers are equal or alias each
397 /// other. The registers may be virtual register.
398 bool regsOverlap(unsigned regA, unsigned regB) const {
402 if (isVirtualRegister(regA) || isVirtualRegister(regB))
404 return areAliases(regA, regB);
407 /// isSubRegister - Returns true if regB is a sub-register of regA.
409 bool isSubRegister(unsigned regA, unsigned regB) const {
410 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
411 if (*SR == regB) return true;
415 /// isSuperRegister - Returns true if regB is a super-register of regA.
417 bool isSuperRegister(unsigned regA, unsigned regB) const {
418 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
419 if (*SR == regB) return true;
423 /// getCalleeSavedRegs - Return a null-terminated list of all of the
424 /// callee saved registers on this target. The register should be in the
425 /// order of desired callee-save stack frame offset. The first register is
426 /// closed to the incoming stack pointer if stack grows down, and vice versa.
427 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
430 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
431 /// register classes to spill each callee saved register with. The order and
432 /// length of this list match the getCalleeSaveRegs() list.
433 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
434 const MachineFunction *MF) const =0;
436 /// getReservedRegs - Returns a bitset indexed by physical register number
437 /// indicating if a register is a special register that has particular uses
438 /// and should be considered unavailable at all times, e.g. SP, RA. This is
439 /// used by register scavenger to determine what registers are free.
440 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
442 /// getSubReg - Returns the physical register number of sub-register "Index"
443 /// for physical register RegNo.
444 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
446 //===--------------------------------------------------------------------===//
447 // Register Class Information
450 /// Register class iterators
452 regclass_iterator regclass_begin() const { return RegClassBegin; }
453 regclass_iterator regclass_end() const { return RegClassEnd; }
455 unsigned getNumRegClasses() const {
456 return regclass_end()-regclass_begin();
459 /// getRegClass - Returns the register class associated with the enumeration
460 /// value. See class TargetOperandInfo.
461 const TargetRegisterClass *getRegClass(unsigned i) const {
462 assert(i <= getNumRegClasses() && "Register Class ID out of range");
463 return i ? RegClassBegin[i - 1] : NULL;
466 //===--------------------------------------------------------------------===//
467 // Interfaces used by the register allocator and stack frame
468 // manipulation passes to move data around between registers,
469 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
472 /// getCrossCopyRegClass - Returns a legal register class to copy a register
473 /// in the specified class to or from. Returns NULL if it is possible to copy
474 /// between a two registers of the specified class.
475 virtual const TargetRegisterClass *
476 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
480 /// reMaterialize - Re-issue the specified 'original' instruction at the
481 /// specific location targeting a new destination register.
482 virtual void reMaterialize(MachineBasicBlock &MBB,
483 MachineBasicBlock::iterator MI,
485 const MachineInstr *Orig) const = 0;
487 /// targetHandlesStackFrameRounding - Returns true if the target is
488 /// responsible for rounding up the stack frame (probably at emitPrologue
490 virtual bool targetHandlesStackFrameRounding() const {
494 /// requiresRegisterScavenging - returns true if the target requires (and can
495 /// make use of) the register scavenger.
496 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
500 /// hasFP - Return true if the specified function should have a dedicated
501 /// frame pointer register. For most targets this is true only if the function
502 /// has variable sized allocas or if frame pointer elimination is disabled.
503 virtual bool hasFP(const MachineFunction &MF) const = 0;
505 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
506 // not required, we reserve argument space for call sites in the function
507 // immediately on entry to the current function. This eliminates the need for
508 // add/sub sp brackets around call sites. Returns true if the call frame is
509 // included as part of the stack frame.
510 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
514 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
515 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
516 /// targets use pseudo instructions in order to abstract away the difference
517 /// between operating with a frame pointer and operating without, through the
518 /// use of these two instructions.
520 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
521 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
524 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
525 /// code insertion to eliminate call frame setup and destroy pseudo
526 /// instructions (but only if the Target is using them). It is responsible
527 /// for eliminating these instructions, replacing them with concrete
528 /// instructions. This method need only be implemented if using call frame
529 /// setup/destroy pseudo instructions.
532 eliminateCallFramePseudoInstr(MachineFunction &MF,
533 MachineBasicBlock &MBB,
534 MachineBasicBlock::iterator MI) const {
535 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
536 "eliminateCallFramePseudoInstr must be implemented if using"
537 " call frame setup/destroy pseudo instructions!");
538 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
541 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
542 /// before PrologEpilogInserter scans the physical registers used to determine
543 /// what callee saved registers should be spilled. This method is optional.
544 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
545 RegScavenger *RS = NULL) const {
549 /// processFunctionBeforeFrameFinalized - This method is called immediately
550 /// before the specified functions frame layout (MF.getFrameInfo()) is
551 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
552 /// replaced with direct constants. This method is optional.
554 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
557 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
558 /// frame indices from instructions which may use them. The instruction
559 /// referenced by the iterator contains an MO_FrameIndex operand which must be
560 /// eliminated by this method. This method may modify or replace the
561 /// specified instruction, as long as it keeps the iterator pointing the the
562 /// finished product. SPAdj is the SP adjustment due to call frame setup
563 /// instruction. The return value is the number of instructions added to
564 /// (negative if removed from) the basic block.
566 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
567 int SPAdj, RegScavenger *RS=NULL) const = 0;
569 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
570 /// the function. The return value is the number of instructions
571 /// added to (negative if removed from) the basic block (entry for prologue).
573 virtual void emitPrologue(MachineFunction &MF) const = 0;
574 virtual void emitEpilogue(MachineFunction &MF,
575 MachineBasicBlock &MBB) const = 0;
577 //===--------------------------------------------------------------------===//
578 /// Debug information queries.
580 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
581 /// number. Returns -1 if there is no equivalent value. The second
582 /// parameter allows targets to use different numberings for EH info and
584 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
586 /// getFrameRegister - This method should return the register used as a base
587 /// for values allocated in the current stack frame.
588 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
590 /// getRARegister - This method should return the register where the return
591 /// address can be found.
592 virtual unsigned getRARegister() const = 0;
594 /// getLocation - This method should return the actual location of a frame
595 /// variable given the frame index. The location is returned in ML.
596 /// Subclasses should override this method for special handling of frame
597 /// variables and call MRegisterInfo::getLocation for the default action.
598 virtual void getLocation(MachineFunction &MF, unsigned Index,
599 MachineLocation &ML) const;
601 /// getInitialFrameState - Returns a list of machine moves that are assumed
602 /// on entry to all functions. Note that LabelID is ignored (assumed to be
603 /// the beginning of the function.)
604 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
607 // This is useful when building IndexedMaps keyed on virtual registers
608 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
609 unsigned operator()(unsigned Reg) const {
610 return Reg - MRegisterInfo::FirstVirtualRegister;
614 } // End llvm namespace