1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
28 class MachineFunction;
34 class TargetRegisterClass;
37 /// TargetRegisterDesc - This record contains all of the information known about
38 /// a particular register. The AliasSet field (if not null) contains a pointer
39 /// to a Zero terminated array of registers that this register aliases. This is
40 /// needed for architectures like X86 which have AL alias AX alias EAX.
41 /// Registers that this does not apply to simply should set this to null.
42 /// The SubRegs field is a zero terminated array of registers that are
43 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
44 /// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
45 /// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
46 /// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
47 /// terminated array of registers that are super-registers of the specific
48 /// register, e.g. RAX, EAX, are super-registers of AX.
50 struct TargetRegisterDesc {
51 const char *Name; // Assembly language name for the register
52 const unsigned *AliasSet; // Register Alias Set, described above
53 const unsigned *SubRegs; // Sub-register set, described above
54 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
55 const unsigned *SuperRegs; // Super-register set, described above
58 class TargetRegisterClass {
60 typedef const unsigned* iterator;
61 typedef const unsigned* const_iterator;
63 typedef const MVT::ValueType* vt_iterator;
64 typedef const TargetRegisterClass* const * sc_iterator;
68 const vt_iterator VTs;
69 const sc_iterator SubClasses;
70 const sc_iterator SuperClasses;
71 const sc_iterator SubRegClasses;
72 const sc_iterator SuperRegClasses;
73 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
75 const iterator RegsBegin, RegsEnd;
77 TargetRegisterClass(unsigned id,
78 const MVT::ValueType *vts,
79 const TargetRegisterClass * const *subcs,
80 const TargetRegisterClass * const *supcs,
81 const TargetRegisterClass * const *subregcs,
82 const TargetRegisterClass * const *superregcs,
83 unsigned RS, unsigned Al, int CC,
84 iterator RB, iterator RE)
85 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
86 SubRegClasses(subregcs), SuperRegClasses(superregcs),
87 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
88 virtual ~TargetRegisterClass() {} // Allow subclasses
90 /// getID() - Return the register class ID number.
92 unsigned getID() const { return ID; }
94 /// begin/end - Return all of the registers in this class.
96 iterator begin() const { return RegsBegin; }
97 iterator end() const { return RegsEnd; }
99 /// getNumRegs - Return the number of registers in this class.
101 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
103 /// getRegister - Return the specified register in the class.
105 unsigned getRegister(unsigned i) const {
106 assert(i < getNumRegs() && "Register number out of range!");
110 /// contains - Return true if the specified register is included in this
112 bool contains(unsigned Reg) const {
113 for (iterator I = begin(), E = end(); I != E; ++I)
114 if (*I == Reg) return true;
118 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
120 bool hasType(MVT::ValueType vt) const {
121 for(int i = 0; VTs[i] != MVT::Other; ++i)
127 /// vt_begin / vt_end - Loop over all of the value types that can be
128 /// represented by values in this register class.
129 vt_iterator vt_begin() const {
133 vt_iterator vt_end() const {
135 while (*I != MVT::Other) ++I;
139 /// hasSubClass - return true if the specified TargetRegisterClass is a
140 /// sub-register class of this TargetRegisterClass.
141 bool hasSubClass(const TargetRegisterClass *cs) const {
142 for (int i = 0; SubClasses[i] != NULL; ++i)
143 if (SubClasses[i] == cs)
148 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
149 /// this register class.
150 sc_iterator subclasses_begin() const {
154 sc_iterator subclasses_end() const {
155 sc_iterator I = SubClasses;
156 while (*I != NULL) ++I;
160 /// hasSuperClass - return true if the specified TargetRegisterClass is a
161 /// super-register class of this TargetRegisterClass.
162 bool hasSuperClass(const TargetRegisterClass *cs) const {
163 for (int i = 0; SuperClasses[i] != NULL; ++i)
164 if (SuperClasses[i] == cs)
169 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
170 /// of this register class.
171 sc_iterator superclasses_begin() const {
175 sc_iterator superclasses_end() const {
176 sc_iterator I = SuperClasses;
177 while (*I != NULL) ++I;
181 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
182 /// class of a sub-register class for this TargetRegisterClass.
183 bool hasSubRegClass(const TargetRegisterClass *cs) const {
184 for (int i = 0; SubRegClasses[i] != NULL; ++i)
185 if (SubRegClasses[i] == cs)
190 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
191 /// class of a sub-register class for this TargetRegisterClass.
192 bool hasClassForSubReg(unsigned SubReg) const {
194 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
200 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
201 /// at idx for this TargetRegisterClass.
202 sc_iterator getClassForSubReg(unsigned SubReg) const {
204 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
206 return &SubRegClasses[i];
207 assert(0 && "Invalid subregister index for register class");
211 /// subregclasses_begin / subregclasses_end - Loop over all of
212 /// the subregister classes of this register class.
213 sc_iterator subregclasses_begin() const {
214 return SubRegClasses;
217 sc_iterator subregclasses_end() const {
218 sc_iterator I = SubRegClasses;
219 while (*I != NULL) ++I;
223 /// superregclasses_begin / superregclasses_end - Loop over all of
224 /// the superregister classes of this register class.
225 sc_iterator superregclasses_begin() const {
226 return SuperRegClasses;
229 sc_iterator superregclasses_end() const {
230 sc_iterator I = SuperRegClasses;
231 while (*I != NULL) ++I;
235 /// allocation_order_begin/end - These methods define a range of registers
236 /// which specify the registers in this class that are valid to register
237 /// allocate, and the preferred order to allocate them in. For example,
238 /// callee saved registers should be at the end of the list, because it is
239 /// cheaper to allocate caller saved registers.
241 /// These methods take a MachineFunction argument, which can be used to tune
242 /// the allocatable registers based on the characteristics of the function.
243 /// One simple example is that the frame pointer register can be used if
244 /// frame-pointer-elimination is performed.
246 /// By default, these methods return all registers in the class.
248 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
251 virtual iterator allocation_order_end(const MachineFunction &MF) const {
257 /// getSize - Return the size of the register in bytes, which is also the size
258 /// of a stack slot allocated to hold a spilled copy of this register.
259 unsigned getSize() const { return RegSize; }
261 /// getAlignment - Return the minimum required alignment for a register of
263 unsigned getAlignment() const { return Alignment; }
265 /// getCopyCost - Return the cost of copying a value between two registers in
267 int getCopyCost() const { return CopyCost; }
271 /// MRegisterInfo base class - We assume that the target defines a static array
272 /// of TargetRegisterDesc objects that represent all of the machine registers
273 /// that the target has. As such, we simply have to track a pointer to this
274 /// array so that we can turn register number into a register descriptor.
276 class MRegisterInfo {
278 typedef const TargetRegisterClass * const * regclass_iterator;
280 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
281 unsigned NumRegs; // Number of entries in the array
283 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
285 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
287 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
288 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
289 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
290 virtual ~MRegisterInfo();
293 enum { // Define some target independent constants
294 /// NoRegister - This physical register is not a real target register. It
295 /// is useful as a sentinal.
298 /// FirstVirtualRegister - This is the first register number that is
299 /// considered to be a 'virtual' register, which is part of the SSA
300 /// namespace. This must be the same for all targets, which means that each
301 /// target is limited to 1024 registers.
302 FirstVirtualRegister = 1024
305 /// isPhysicalRegister - Return true if the specified register number is in
306 /// the physical register namespace.
307 static bool isPhysicalRegister(unsigned Reg) {
308 assert(Reg && "this is not a register!");
309 return Reg < FirstVirtualRegister;
312 /// isVirtualRegister - Return true if the specified register number is in
313 /// the virtual register namespace.
314 static bool isVirtualRegister(unsigned Reg) {
315 assert(Reg && "this is not a register!");
316 return Reg >= FirstVirtualRegister;
319 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
320 /// register of the given type.
321 const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
324 /// getAllocatableSet - Returns a bitset indexed by register number
325 /// indicating if a register is allocatable or not. If a register class is
326 /// specified, returns the subset for the class.
327 BitVector getAllocatableSet(MachineFunction &MF,
328 const TargetRegisterClass *RC = NULL) const;
330 const TargetRegisterDesc &operator[](unsigned RegNo) const {
331 assert(RegNo < NumRegs &&
332 "Attempting to access record for invalid register number!");
336 /// Provide a get method, equivalent to [], but more useful if we have a
337 /// pointer to this object.
339 const TargetRegisterDesc &get(unsigned RegNo) const {
340 return operator[](RegNo);
343 /// getAliasSet - Return the set of registers aliased by the specified
344 /// register, or a null list of there are none. The list returned is zero
347 const unsigned *getAliasSet(unsigned RegNo) const {
348 return get(RegNo).AliasSet;
351 /// getSubRegisters - Return the set of registers that are sub-registers of
352 /// the specified register, or a null list of there are none. The list
353 /// returned is zero terminated.
355 const unsigned *getSubRegisters(unsigned RegNo) const {
356 return get(RegNo).SubRegs;
359 /// getImmediateSubRegisters - Return the set of registers that are immediate
360 /// sub-registers of the specified register, or a null list of there are none.
361 /// The list returned is zero terminated.
363 const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
364 return get(RegNo).ImmSubRegs;
367 /// getSuperRegisters - Return the set of registers that are super-registers
368 /// of the specified register, or a null list of there are none. The list
369 /// returned is zero terminated.
371 const unsigned *getSuperRegisters(unsigned RegNo) const {
372 return get(RegNo).SuperRegs;
375 /// getName - Return the symbolic target specific name for the specified
376 /// physical register.
377 const char *getName(unsigned RegNo) const {
378 return get(RegNo).Name;
381 /// getNumRegs - Return the number of registers this target has (useful for
382 /// sizing arrays holding per register information)
383 unsigned getNumRegs() const {
387 /// areAliases - Returns true if the two registers alias each other, false
389 bool areAliases(unsigned regA, unsigned regB) const {
390 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
391 if (*Alias == regB) return true;
395 /// regsOverlap - Returns true if the two registers are equal or alias each
396 /// other. The registers may be virtual register.
397 bool regsOverlap(unsigned regA, unsigned regB) const {
401 if (isVirtualRegister(regA) || isVirtualRegister(regB))
403 return areAliases(regA, regB);
406 /// isSubRegister - Returns true if regB is a sub-register of regA.
408 bool isSubRegister(unsigned regA, unsigned regB) const {
409 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
410 if (*SR == regB) return true;
414 /// isSuperRegister - Returns true if regB is a super-register of regA.
416 bool isSuperRegister(unsigned regA, unsigned regB) const {
417 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
418 if (*SR == regB) return true;
422 /// getCalleeSavedRegs - Return a null-terminated list of all of the
423 /// callee saved registers on this target. The register should be in the
424 /// order of desired callee-save stack frame offset. The first register is
425 /// closed to the incoming stack pointer if stack grows down, and vice versa.
426 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
429 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
430 /// register classes to spill each callee saved register with. The order and
431 /// length of this list match the getCalleeSaveRegs() list.
432 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
433 const MachineFunction *MF) const =0;
435 /// getReservedRegs - Returns a bitset indexed by physical register number
436 /// indicating if a register is a special register that has particular uses
437 /// and should be considered unavailable at all times, e.g. SP, RA. This is
438 /// used by register scavenger to determine what registers are free.
439 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
441 /// getSubReg - Returns the physical register number of sub-register "Index"
442 /// for physical register RegNo.
443 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
445 //===--------------------------------------------------------------------===//
446 // Register Class Information
449 /// Register class iterators
451 regclass_iterator regclass_begin() const { return RegClassBegin; }
452 regclass_iterator regclass_end() const { return RegClassEnd; }
454 unsigned getNumRegClasses() const {
455 return regclass_end()-regclass_begin();
458 /// getRegClass - Returns the register class associated with the enumeration
459 /// value. See class TargetOperandInfo.
460 const TargetRegisterClass *getRegClass(unsigned i) const {
461 assert(i <= getNumRegClasses() && "Register Class ID out of range");
462 return i ? RegClassBegin[i - 1] : NULL;
465 //===--------------------------------------------------------------------===//
466 // Interfaces used by the register allocator and stack frame
467 // manipulation passes to move data around between registers,
468 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
471 /// getCrossCopyRegClass - Returns a legal register class to copy a register
472 /// in the specified class to or from. Returns NULL if it is possible to copy
473 /// between a two registers of the specified class.
474 virtual const TargetRegisterClass *
475 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
479 /// reMaterialize - Re-issue the specified 'original' instruction at the
480 /// specific location targeting a new destination register.
481 virtual void reMaterialize(MachineBasicBlock &MBB,
482 MachineBasicBlock::iterator MI,
484 const MachineInstr *Orig) const = 0;
486 /// targetHandlesStackFrameRounding - Returns true if the target is
487 /// responsible for rounding up the stack frame (probably at emitPrologue
489 virtual bool targetHandlesStackFrameRounding() const {
493 /// requiresRegisterScavenging - returns true if the target requires (and can
494 /// make use of) the register scavenger.
495 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
499 /// hasFP - Return true if the specified function should have a dedicated
500 /// frame pointer register. For most targets this is true only if the function
501 /// has variable sized allocas or if frame pointer elimination is disabled.
502 virtual bool hasFP(const MachineFunction &MF) const = 0;
504 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
505 // not required, we reserve argument space for call sites in the function
506 // immediately on entry to the current function. This eliminates the need for
507 // add/sub sp brackets around call sites. Returns true if the call frame is
508 // included as part of the stack frame.
509 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
513 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
514 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
515 /// targets use pseudo instructions in order to abstract away the difference
516 /// between operating with a frame pointer and operating without, through the
517 /// use of these two instructions.
519 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
520 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
523 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
524 /// code insertion to eliminate call frame setup and destroy pseudo
525 /// instructions (but only if the Target is using them). It is responsible
526 /// for eliminating these instructions, replacing them with concrete
527 /// instructions. This method need only be implemented if using call frame
528 /// setup/destroy pseudo instructions.
531 eliminateCallFramePseudoInstr(MachineFunction &MF,
532 MachineBasicBlock &MBB,
533 MachineBasicBlock::iterator MI) const {
534 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
535 "eliminateCallFramePseudoInstr must be implemented if using"
536 " call frame setup/destroy pseudo instructions!");
537 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
540 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
541 /// before PrologEpilogInserter scans the physical registers used to determine
542 /// what callee saved registers should be spilled. This method is optional.
543 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
544 RegScavenger *RS = NULL) const {
548 /// processFunctionBeforeFrameFinalized - This method is called immediately
549 /// before the specified functions frame layout (MF.getFrameInfo()) is
550 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
551 /// replaced with direct constants. This method is optional.
553 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
556 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
557 /// frame indices from instructions which may use them. The instruction
558 /// referenced by the iterator contains an MO_FrameIndex operand which must be
559 /// eliminated by this method. This method may modify or replace the
560 /// specified instruction, as long as it keeps the iterator pointing the the
561 /// finished product. SPAdj is the SP adjustment due to call frame setup
562 /// instruction. The return value is the number of instructions added to
563 /// (negative if removed from) the basic block.
565 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
566 int SPAdj, RegScavenger *RS=NULL) const = 0;
568 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
569 /// the function. The return value is the number of instructions
570 /// added to (negative if removed from) the basic block (entry for prologue).
572 virtual void emitPrologue(MachineFunction &MF) const = 0;
573 virtual void emitEpilogue(MachineFunction &MF,
574 MachineBasicBlock &MBB) const = 0;
576 //===--------------------------------------------------------------------===//
577 /// Debug information queries.
579 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
580 /// number. Returns -1 if there is no equivalent value. The second
581 /// parameter allows targets to use different numberings for EH info and
583 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
585 /// getFrameRegister - This method should return the register used as a base
586 /// for values allocated in the current stack frame.
587 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
589 /// getFrameIndexOffset - Returns the displacement from the frame register to
590 /// the stack frame of the specified index.
591 virtual int getFrameIndexOffset(MachineFunction &MF, unsigned FI) const;
593 /// getRARegister - This method should return the register where the return
594 /// address can be found.
595 virtual unsigned getRARegister() const = 0;
597 /// getInitialFrameState - Returns a list of machine moves that are assumed
598 /// on entry to all functions. Note that LabelID is ignored (assumed to be
599 /// the beginning of the function.)
600 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
603 // This is useful when building IndexedMaps keyed on virtual registers
604 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
605 unsigned operator()(unsigned Reg) const {
606 return Reg - MRegisterInfo::FirstVirtualRegister;
610 } // End llvm namespace