1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class TargetRegisterClass;
31 /// TargetRegisterDesc - This record contains all of the information known about
32 /// a particular register. The AliasSet field (if not null) contains a pointer
33 /// to a Zero terminated array of registers that this register aliases. This is
34 /// needed for architectures like X86 which have AL alias AX alias EAX.
35 /// Registers that this does not apply to simply should set this to null.
37 struct TargetRegisterDesc {
38 const char *Name; // Assembly language name for the register
39 const unsigned *AliasSet; // Register Alias Set, described above
42 class TargetRegisterClass {
44 typedef const unsigned* iterator;
45 typedef const unsigned* const_iterator;
48 const MVT::ValueType VT;
49 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
50 const iterator RegsBegin, RegsEnd;
52 TargetRegisterClass(MVT::ValueType vt, unsigned RS, unsigned Al, iterator RB, iterator RE)
53 : VT(vt), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
54 virtual ~TargetRegisterClass() {} // Allow subclasses
56 /// getType - Return the declared value type for this register class.
58 MVT::ValueType getType() const { return VT; }
60 // begin/end - Return all of the registers in this class.
61 iterator begin() const { return RegsBegin; }
62 iterator end() const { return RegsEnd; }
64 // getNumRegs - Return the number of registers in this class
65 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
67 // getRegister - Return the specified register in the class
68 unsigned getRegister(unsigned i) const {
69 assert(i < getNumRegs() && "Register number out of range!");
73 /// contains - Return true if the specified register is included in this
75 bool contains(unsigned Reg) const {
76 for (iterator I = begin(), E = end(); I != E; ++I)
77 if (*I == Reg) return true;
81 /// allocation_order_begin/end - These methods define a range of registers
82 /// which specify the registers in this class that are valid to register
83 /// allocate, and the preferred order to allocate them in. For example,
84 /// callee saved registers should be at the end of the list, because it is
85 /// cheaper to allocate caller saved registers.
87 /// These methods take a MachineFunction argument, which can be used to tune
88 /// the allocatable registers based on the characteristics of the function.
89 /// One simple example is that the frame pointer register can be used if
90 /// frame-pointer-elimination is performed.
92 /// By default, these methods return all registers in the class.
94 virtual iterator allocation_order_begin(MachineFunction &MF) const {
97 virtual iterator allocation_order_end(MachineFunction &MF) const {
103 /// getSize - Return the size of the register in bytes, which is also the size
104 /// of a stack slot allocated to hold a spilled copy of this register.
105 unsigned getSize() const { return RegSize; }
107 /// getAlignment - Return the minimum required alignment for a register of
109 unsigned getAlignment() const { return Alignment; }
113 /// MRegisterInfo base class - We assume that the target defines a static array
114 /// of TargetRegisterDesc objects that represent all of the machine registers
115 /// that the target has. As such, we simply have to track a pointer to this
116 /// array so that we can turn register number into a register descriptor.
118 class MRegisterInfo {
120 typedef const TargetRegisterClass * const * regclass_iterator;
122 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
123 unsigned NumRegs; // Number of entries in the array
125 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
127 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
129 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
130 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
131 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
132 virtual ~MRegisterInfo();
135 enum { // Define some target independent constants
136 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
137 /// This is used as the destination register for instructions that do not
138 /// produce a value. Some frontends may use this as an operand register to
139 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
140 /// which always PRODUCES the value 0. The X86 backend does not use this
141 /// value as an operand register, except for memory references.
145 /// FirstVirtualRegister - This is the first register number that is
146 /// considered to be a 'virtual' register, which is part of the SSA
147 /// namespace. This must be the same for all targets, which means that each
148 /// target is limited to 1024 registers.
150 FirstVirtualRegister = 1024,
153 /// isPhysicalRegister - Return true if the specified register number is in
154 /// the physical register namespace.
155 static bool isPhysicalRegister(unsigned Reg) {
156 assert(Reg && "this is not a register!");
157 return Reg < FirstVirtualRegister;
160 /// isVirtualRegister - Return true if the specified register number is in
161 /// the virtual register namespace.
162 static bool isVirtualRegister(unsigned Reg) {
163 assert(Reg && "this is not a register!");
164 return Reg >= FirstVirtualRegister;
167 /// getAllocatableSet - Returns a bitset indexed by register number
168 /// indicating if a register is allocatable or not.
169 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
171 const TargetRegisterDesc &operator[](unsigned RegNo) const {
172 assert(RegNo < NumRegs &&
173 "Attempting to access record for invalid register number!");
177 /// Provide a get method, equivalent to [], but more useful if we have a
178 /// pointer to this object.
180 const TargetRegisterDesc &get(unsigned RegNo) const {
181 return operator[](RegNo);
184 /// getAliasSet - Return the set of registers aliased by the specified
185 /// register, or a null list of there are none. The list returned is zero
188 const unsigned *getAliasSet(unsigned RegNo) const {
189 return get(RegNo).AliasSet;
192 /// getName - Return the symbolic target specific name for the specified
193 /// physical register.
194 const char *getName(unsigned RegNo) const {
195 return get(RegNo).Name;
198 /// getNumRegs - Return the number of registers this target has
199 /// (useful for sizing arrays holding per register information)
200 unsigned getNumRegs() const {
204 /// areAliases - Returns true if the two registers alias each other,
206 bool areAliases(unsigned regA, unsigned regB) const {
207 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
208 if (*Alias == regB) return true;
212 /// getCalleeSaveRegs - Return a null-terminated list of all of the
213 /// callee-save registers on this target.
214 virtual const unsigned* getCalleeSaveRegs() const = 0;
216 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
217 /// register classes to spill each callee-saved register with. The order and
218 /// length of this list match the getCalleeSaveRegs() list.
219 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
221 //===--------------------------------------------------------------------===//
222 // Register Class Information
225 /// Register class iterators
227 regclass_iterator regclass_begin() const { return RegClassBegin; }
228 regclass_iterator regclass_end() const { return RegClassEnd; }
230 unsigned getNumRegClasses() const {
231 return regclass_end()-regclass_begin();
234 //===--------------------------------------------------------------------===//
235 // Interfaces used by the register allocator and stack frame
236 // manipulation passes to move data around between registers,
237 // immediates and memory. The return value is the number of
238 // instructions added to (negative if removed from) the basic block.
241 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
242 MachineBasicBlock::iterator MI,
243 unsigned SrcReg, int FrameIndex,
244 const TargetRegisterClass *RC) const = 0;
246 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
247 MachineBasicBlock::iterator MI,
248 unsigned DestReg, int FrameIndex,
249 const TargetRegisterClass *RC) const = 0;
251 virtual void copyRegToReg(MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator MI,
253 unsigned DestReg, unsigned SrcReg,
254 const TargetRegisterClass *RC) const = 0;
256 /// isLoadFromStackSlot - If the specified machine instruction is a direct
257 /// load from a stack slot, return the virtual or physical register number of
258 /// the destination along with the FrameIndex of the loaded stack slot. If
259 /// not, return 0. This predicate must return false if the instruction has
260 /// any side effects other than loading from the stack slot.
261 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
265 /// foldMemoryOperand - Attempt to fold a load or store of the
266 /// specified stack slot into the specified machine instruction for
267 /// the specified operand. If this is possible, a new instruction
268 /// is returned with the specified operand folded, otherwise NULL is
269 /// returned. The client is responsible for removing the old
270 /// instruction and adding the new one in the instruction stream
271 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
273 int FrameIndex) const {
277 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
278 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
279 /// targets use pseudo instructions in order to abstract away the difference
280 /// between operating with a frame pointer and operating without, through the
281 /// use of these two instructions.
283 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
284 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
287 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
288 /// code insertion to eliminate call frame setup and destroy pseudo
289 /// instructions (but only if the Target is using them). It is responsible
290 /// for eliminating these instructions, replacing them with concrete
291 /// instructions. This method need only be implemented if using call frame
292 /// setup/destroy pseudo instructions.
295 eliminateCallFramePseudoInstr(MachineFunction &MF,
296 MachineBasicBlock &MBB,
297 MachineBasicBlock::iterator MI) const {
298 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
299 "eliminateCallFramePseudoInstr must be implemented if using"
300 " call frame setup/destroy pseudo instructions!");
301 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
304 /// processFunctionBeforeFrameFinalized - This method is called immediately
305 /// before the specified functions frame layout (MF.getFrameInfo()) is
306 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
307 /// replaced with direct constants. This method is optional. The return value
308 /// is the number of instructions added to (negative if removed from) the
311 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
314 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
315 /// frame indices from instructions which may use them. The instruction
316 /// referenced by the iterator contains an MO_FrameIndex operand which must be
317 /// eliminated by this method. This method may modify or replace the
318 /// specified instruction, as long as it keeps the iterator pointing the the
319 /// finished product. The return value is the number of instructions
320 /// added to (negative if removed from) the basic block.
322 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
324 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
325 /// the function. The return value is the number of instructions
326 /// added to (negative if removed from) the basic block (entry for prologue).
328 virtual void emitPrologue(MachineFunction &MF) const = 0;
329 virtual void emitEpilogue(MachineFunction &MF,
330 MachineBasicBlock &MBB) const = 0;
333 // This is useful when building DenseMaps keyed on virtual registers
334 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
335 unsigned operator()(unsigned Reg) const {
336 return Reg - MRegisterInfo::FirstVirtualRegister;
340 } // End llvm namespace