1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class MachineLocation;
31 class TargetRegisterClass;
32 class CalleeSavedInfo;
34 /// TargetRegisterDesc - This record contains all of the information known about
35 /// a particular register. The AliasSet field (if not null) contains a pointer
36 /// to a Zero terminated array of registers that this register aliases. This is
37 /// needed for architectures like X86 which have AL alias AX alias EAX.
38 /// Registers that this does not apply to simply should set this to null.
40 struct TargetRegisterDesc {
41 const char *Name; // Assembly language name for the register
42 const unsigned *AliasSet; // Register Alias Set, described above
45 class TargetRegisterClass {
47 typedef const unsigned* iterator;
48 typedef const unsigned* const_iterator;
50 typedef const MVT::ValueType* vt_iterator;
51 typedef const TargetRegisterClass* const * sc_iterator;
55 const vt_iterator VTs;
56 const sc_iterator SubClasses;
57 const sc_iterator SuperClasses;
58 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
59 const iterator RegsBegin, RegsEnd;
61 TargetRegisterClass(unsigned id,
62 const MVT::ValueType *vts,
63 const TargetRegisterClass * const *subcs,
64 const TargetRegisterClass * const *supcs,
65 unsigned RS, unsigned Al, iterator RB, iterator RE)
66 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
67 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
68 virtual ~TargetRegisterClass() {} // Allow subclasses
70 /// getID() - Return the register class ID number.
72 unsigned getID() const { return ID; }
74 /// begin/end - Return all of the registers in this class.
76 iterator begin() const { return RegsBegin; }
77 iterator end() const { return RegsEnd; }
79 /// getNumRegs - Return the number of registers in this class.
81 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
83 /// getRegister - Return the specified register in the class.
85 unsigned getRegister(unsigned i) const {
86 assert(i < getNumRegs() && "Register number out of range!");
90 /// contains - Return true if the specified register is included in this
92 bool contains(unsigned Reg) const {
93 for (iterator I = begin(), E = end(); I != E; ++I)
94 if (*I == Reg) return true;
98 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
100 bool hasType(MVT::ValueType vt) const {
101 for(int i = 0; VTs[i] != MVT::Other; ++i)
107 /// vt_begin / vt_end - Loop over all of the value types that can be
108 /// represented by values in this register class.
109 vt_iterator vt_begin() const {
113 vt_iterator vt_end() const {
115 while (*I != MVT::Other) ++I;
119 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
120 /// sub-register class of this TargetRegisterClass.
121 bool hasSubRegClass(const TargetRegisterClass *cs) const {
122 for (int i = 0; SubClasses[i] != NULL; ++i)
123 if (SubClasses[i] == cs)
128 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
129 /// this register class.
130 sc_iterator subclasses_begin() const {
134 sc_iterator subclasses_end() const {
135 sc_iterator I = SubClasses;
136 while (*I != NULL) ++I;
140 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
141 /// super-register class of this TargetRegisterClass.
142 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
143 for (int i = 0; SuperClasses[i] != NULL; ++i)
144 if (SuperClasses[i] == cs)
149 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
150 /// of this register class.
151 sc_iterator superclasses_begin() const {
155 sc_iterator superclasses_end() const {
156 sc_iterator I = SuperClasses;
157 while (*I != NULL) ++I;
161 /// allocation_order_begin/end - These methods define a range of registers
162 /// which specify the registers in this class that are valid to register
163 /// allocate, and the preferred order to allocate them in. For example,
164 /// callee saved registers should be at the end of the list, because it is
165 /// cheaper to allocate caller saved registers.
167 /// These methods take a MachineFunction argument, which can be used to tune
168 /// the allocatable registers based on the characteristics of the function.
169 /// One simple example is that the frame pointer register can be used if
170 /// frame-pointer-elimination is performed.
172 /// By default, these methods return all registers in the class.
174 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
177 virtual iterator allocation_order_end(const MachineFunction &MF) const {
183 /// getSize - Return the size of the register in bytes, which is also the size
184 /// of a stack slot allocated to hold a spilled copy of this register.
185 unsigned getSize() const { return RegSize; }
187 /// getAlignment - Return the minimum required alignment for a register of
189 unsigned getAlignment() const { return Alignment; }
193 /// MRegisterInfo base class - We assume that the target defines a static array
194 /// of TargetRegisterDesc objects that represent all of the machine registers
195 /// that the target has. As such, we simply have to track a pointer to this
196 /// array so that we can turn register number into a register descriptor.
198 class MRegisterInfo {
200 typedef const TargetRegisterClass * const * regclass_iterator;
202 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
203 unsigned NumRegs; // Number of entries in the array
205 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
207 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
209 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
210 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
211 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
212 virtual ~MRegisterInfo();
215 enum { // Define some target independent constants
216 /// NoRegister - This physical register is not a real target register. It
217 /// is useful as a sentinal.
220 /// FirstVirtualRegister - This is the first register number that is
221 /// considered to be a 'virtual' register, which is part of the SSA
222 /// namespace. This must be the same for all targets, which means that each
223 /// target is limited to 1024 registers.
224 FirstVirtualRegister = 1024
227 /// isPhysicalRegister - Return true if the specified register number is in
228 /// the physical register namespace.
229 static bool isPhysicalRegister(unsigned Reg) {
230 assert(Reg && "this is not a register!");
231 return Reg < FirstVirtualRegister;
234 /// isVirtualRegister - Return true if the specified register number is in
235 /// the virtual register namespace.
236 static bool isVirtualRegister(unsigned Reg) {
237 assert(Reg && "this is not a register!");
238 return Reg >= FirstVirtualRegister;
241 /// getAllocatableSet - Returns a bitset indexed by register number
242 /// indicating if a register is allocatable or not.
243 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
245 const TargetRegisterDesc &operator[](unsigned RegNo) const {
246 assert(RegNo < NumRegs &&
247 "Attempting to access record for invalid register number!");
251 /// Provide a get method, equivalent to [], but more useful if we have a
252 /// pointer to this object.
254 const TargetRegisterDesc &get(unsigned RegNo) const {
255 return operator[](RegNo);
258 /// getAliasSet - Return the set of registers aliased by the specified
259 /// register, or a null list of there are none. The list returned is zero
262 const unsigned *getAliasSet(unsigned RegNo) const {
263 return get(RegNo).AliasSet;
266 /// getName - Return the symbolic target specific name for the specified
267 /// physical register.
268 const char *getName(unsigned RegNo) const {
269 return get(RegNo).Name;
272 /// getNumRegs - Return the number of registers this target has
273 /// (useful for sizing arrays holding per register information)
274 unsigned getNumRegs() const {
278 /// areAliases - Returns true if the two registers alias each other,
280 bool areAliases(unsigned regA, unsigned regB) const {
281 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
282 if (*Alias == regB) return true;
286 /// getCalleeSavedRegs - Return a null-terminated list of all of the
287 /// callee saved registers on this target. The register should be in the
288 /// order of desired callee-save stack frame offset. The first register is
289 /// closed to the incoming stack pointer if stack grows down, and vice versa.
290 virtual const unsigned* getCalleeSavedRegs() const = 0;
292 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
293 /// register classes to spill each callee saved register with. The order and
294 /// length of this list match the getCalleeSaveRegs() list.
295 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
297 //===--------------------------------------------------------------------===//
298 // Register Class Information
301 /// Register class iterators
303 regclass_iterator regclass_begin() const { return RegClassBegin; }
304 regclass_iterator regclass_end() const { return RegClassEnd; }
306 unsigned getNumRegClasses() const {
307 return regclass_end()-regclass_begin();
310 /// getRegClass - Returns the register class associated with the enumeration
311 /// value. See class TargetOperandInfo.
312 const TargetRegisterClass *getRegClass(unsigned i) const {
313 assert(i <= getNumRegClasses() && "Register Class ID out of range");
314 return i ? RegClassBegin[i - 1] : NULL;
317 //===--------------------------------------------------------------------===//
318 // Interfaces used by the register allocator and stack frame
319 // manipulation passes to move data around between registers,
320 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
323 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
324 /// registers and returns true if it isn't possible / profitable to do so by
325 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
327 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
328 MachineBasicBlock::iterator MI,
329 const std::vector<CalleeSavedInfo> &CSI) const {
333 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
334 /// saved registers and returns true if it isn't possible / profitable to do
335 /// so by issuing a series of load instructions via loadRegToStackSlot().
336 /// Returns false otherwise.
337 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
338 MachineBasicBlock::iterator MI,
339 const std::vector<CalleeSavedInfo> &CSI) const {
343 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
344 MachineBasicBlock::iterator MI,
345 unsigned SrcReg, int FrameIndex,
346 const TargetRegisterClass *RC) const = 0;
348 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
349 MachineBasicBlock::iterator MI,
350 unsigned DestReg, int FrameIndex,
351 const TargetRegisterClass *RC) const = 0;
353 virtual void copyRegToReg(MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator MI,
355 unsigned DestReg, unsigned SrcReg,
356 const TargetRegisterClass *RC) const = 0;
358 /// foldMemoryOperand - Attempt to fold a load or store of the
359 /// specified stack slot into the specified machine instruction for
360 /// the specified operand. If this is possible, a new instruction
361 /// is returned with the specified operand folded, otherwise NULL is
362 /// returned. The client is responsible for removing the old
363 /// instruction and adding the new one in the instruction stream
364 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
366 int FrameIndex) const {
370 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
371 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
372 /// targets use pseudo instructions in order to abstract away the difference
373 /// between operating with a frame pointer and operating without, through the
374 /// use of these two instructions.
376 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
377 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
380 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
381 /// code insertion to eliminate call frame setup and destroy pseudo
382 /// instructions (but only if the Target is using them). It is responsible
383 /// for eliminating these instructions, replacing them with concrete
384 /// instructions. This method need only be implemented if using call frame
385 /// setup/destroy pseudo instructions.
388 eliminateCallFramePseudoInstr(MachineFunction &MF,
389 MachineBasicBlock &MBB,
390 MachineBasicBlock::iterator MI) const {
391 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
392 "eliminateCallFramePseudoInstr must be implemented if using"
393 " call frame setup/destroy pseudo instructions!");
394 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
397 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
398 /// before PrologEpilogInserter scans the physical registers used to determine
399 /// what callee saved registers should be spilled. This method is optional.
400 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
403 /// processFunctionBeforeFrameFinalized - This method is called immediately
404 /// before the specified functions frame layout (MF.getFrameInfo()) is
405 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
406 /// replaced with direct constants. This method is optional.
408 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
411 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
412 /// frame indices from instructions which may use them. The instruction
413 /// referenced by the iterator contains an MO_FrameIndex operand which must be
414 /// eliminated by this method. This method may modify or replace the
415 /// specified instruction, as long as it keeps the iterator pointing the the
416 /// finished product. The return value is the number of instructions
417 /// added to (negative if removed from) the basic block.
419 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
421 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
422 /// the function. The return value is the number of instructions
423 /// added to (negative if removed from) the basic block (entry for prologue).
425 virtual void emitPrologue(MachineFunction &MF) const = 0;
426 virtual void emitEpilogue(MachineFunction &MF,
427 MachineBasicBlock &MBB) const = 0;
429 //===--------------------------------------------------------------------===//
430 /// Debug information queries.
432 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
433 /// number. Returns -1 if there is no equivalent value.
434 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
436 /// getFrameRegister - This method should return the register used as a base
437 /// for values allocated in the current stack frame.
438 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
440 /// getRARegister - This method should return the register where the return
441 /// address can be found.
442 virtual unsigned getRARegister() const = 0;
444 /// getLocation - This method should return the actual location of a frame
445 /// variable given the frame index. The location is returned in ML.
446 /// Subclasses should override this method for special handling of frame
447 /// variables and call MRegisterInfo::getLocation for the default action.
448 virtual void getLocation(MachineFunction &MF, unsigned Index,
449 MachineLocation &ML) const;
451 /// getInitialFrameState - Returns a list of machine moves that are assumed
452 /// on entry to all functions. Note that LabelID is ignored (assumed to be
453 /// the beginning of the function.)
454 virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const;
457 // This is useful when building DenseMaps keyed on virtual registers
458 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
459 unsigned operator()(unsigned Reg) const {
460 return Reg - MRegisterInfo::FirstVirtualRegister;
464 } // End llvm namespace