1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class CalleeSavedInfo;
28 class MachineFunction;
30 class MachineLocation;
33 class TargetRegisterClass;
36 /// TargetRegisterDesc - This record contains all of the information known about
37 /// a particular register. The AliasSet field (if not null) contains a pointer
38 /// to a Zero terminated array of registers that this register aliases. This is
39 /// needed for architectures like X86 which have AL alias AX alias EAX.
40 /// Registers that this does not apply to simply should set this to null.
42 struct TargetRegisterDesc {
43 const char *Name; // Assembly language name for the register
44 const unsigned *AliasSet; // Register Alias Set, described above
47 class TargetRegisterClass {
49 typedef const unsigned* iterator;
50 typedef const unsigned* const_iterator;
52 typedef const MVT::ValueType* vt_iterator;
53 typedef const TargetRegisterClass* const * sc_iterator;
57 const vt_iterator VTs;
58 const sc_iterator SubClasses;
59 const sc_iterator SuperClasses;
60 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
61 const iterator RegsBegin, RegsEnd;
63 TargetRegisterClass(unsigned id,
64 const MVT::ValueType *vts,
65 const TargetRegisterClass * const *subcs,
66 const TargetRegisterClass * const *supcs,
67 unsigned RS, unsigned Al, iterator RB, iterator RE)
68 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
69 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
70 virtual ~TargetRegisterClass() {} // Allow subclasses
72 /// getID() - Return the register class ID number.
74 unsigned getID() const { return ID; }
76 /// begin/end - Return all of the registers in this class.
78 iterator begin() const { return RegsBegin; }
79 iterator end() const { return RegsEnd; }
81 /// getNumRegs - Return the number of registers in this class.
83 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
85 /// getRegister - Return the specified register in the class.
87 unsigned getRegister(unsigned i) const {
88 assert(i < getNumRegs() && "Register number out of range!");
92 /// contains - Return true if the specified register is included in this
94 bool contains(unsigned Reg) const {
95 for (iterator I = begin(), E = end(); I != E; ++I)
96 if (*I == Reg) return true;
100 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
102 bool hasType(MVT::ValueType vt) const {
103 for(int i = 0; VTs[i] != MVT::Other; ++i)
109 /// vt_begin / vt_end - Loop over all of the value types that can be
110 /// represented by values in this register class.
111 vt_iterator vt_begin() const {
115 vt_iterator vt_end() const {
117 while (*I != MVT::Other) ++I;
121 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
122 /// sub-register class of this TargetRegisterClass.
123 bool hasSubRegClass(const TargetRegisterClass *cs) const {
124 for (int i = 0; SubClasses[i] != NULL; ++i)
125 if (SubClasses[i] == cs)
130 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
131 /// this register class.
132 sc_iterator subclasses_begin() const {
136 sc_iterator subclasses_end() const {
137 sc_iterator I = SubClasses;
138 while (*I != NULL) ++I;
142 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
143 /// super-register class of this TargetRegisterClass.
144 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
145 for (int i = 0; SuperClasses[i] != NULL; ++i)
146 if (SuperClasses[i] == cs)
151 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
152 /// of this register class.
153 sc_iterator superclasses_begin() const {
157 sc_iterator superclasses_end() const {
158 sc_iterator I = SuperClasses;
159 while (*I != NULL) ++I;
163 /// allocation_order_begin/end - These methods define a range of registers
164 /// which specify the registers in this class that are valid to register
165 /// allocate, and the preferred order to allocate them in. For example,
166 /// callee saved registers should be at the end of the list, because it is
167 /// cheaper to allocate caller saved registers.
169 /// These methods take a MachineFunction argument, which can be used to tune
170 /// the allocatable registers based on the characteristics of the function.
171 /// One simple example is that the frame pointer register can be used if
172 /// frame-pointer-elimination is performed.
174 /// By default, these methods return all registers in the class.
176 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
179 virtual iterator allocation_order_end(const MachineFunction &MF) const {
185 /// getSize - Return the size of the register in bytes, which is also the size
186 /// of a stack slot allocated to hold a spilled copy of this register.
187 unsigned getSize() const { return RegSize; }
189 /// getAlignment - Return the minimum required alignment for a register of
191 unsigned getAlignment() const { return Alignment; }
195 /// MRegisterInfo base class - We assume that the target defines a static array
196 /// of TargetRegisterDesc objects that represent all of the machine registers
197 /// that the target has. As such, we simply have to track a pointer to this
198 /// array so that we can turn register number into a register descriptor.
200 class MRegisterInfo {
202 typedef const TargetRegisterClass * const * regclass_iterator;
204 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
205 unsigned NumRegs; // Number of entries in the array
207 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
209 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
211 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
212 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
213 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
214 virtual ~MRegisterInfo();
217 /// getRegScavenger - Returns pointer to an instance of register scavenger it
218 /// the specific target is making use of one.
219 virtual RegScavenger *getRegScavenger() const {
223 enum { // Define some target independent constants
224 /// NoRegister - This physical register is not a real target register. It
225 /// is useful as a sentinal.
228 /// FirstVirtualRegister - This is the first register number that is
229 /// considered to be a 'virtual' register, which is part of the SSA
230 /// namespace. This must be the same for all targets, which means that each
231 /// target is limited to 1024 registers.
232 FirstVirtualRegister = 1024
235 /// isPhysicalRegister - Return true if the specified register number is in
236 /// the physical register namespace.
237 static bool isPhysicalRegister(unsigned Reg) {
238 assert(Reg && "this is not a register!");
239 return Reg < FirstVirtualRegister;
242 /// isVirtualRegister - Return true if the specified register number is in
243 /// the virtual register namespace.
244 static bool isVirtualRegister(unsigned Reg) {
245 assert(Reg && "this is not a register!");
246 return Reg >= FirstVirtualRegister;
249 /// getAllocatableSet - Returns a bitset indexed by register number
250 /// indicating if a register is allocatable or not.
251 BitVector getAllocatableSet(MachineFunction &MF) const;
253 const TargetRegisterDesc &operator[](unsigned RegNo) const {
254 assert(RegNo < NumRegs &&
255 "Attempting to access record for invalid register number!");
259 /// Provide a get method, equivalent to [], but more useful if we have a
260 /// pointer to this object.
262 const TargetRegisterDesc &get(unsigned RegNo) const {
263 return operator[](RegNo);
266 /// getAliasSet - Return the set of registers aliased by the specified
267 /// register, or a null list of there are none. The list returned is zero
270 const unsigned *getAliasSet(unsigned RegNo) const {
271 return get(RegNo).AliasSet;
274 /// getName - Return the symbolic target specific name for the specified
275 /// physical register.
276 const char *getName(unsigned RegNo) const {
277 return get(RegNo).Name;
280 /// getNumRegs - Return the number of registers this target has
281 /// (useful for sizing arrays holding per register information)
282 unsigned getNumRegs() const {
286 /// areAliases - Returns true if the two registers alias each other,
288 bool areAliases(unsigned regA, unsigned regB) const {
289 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
290 if (*Alias == regB) return true;
294 /// regsOverlap - Returns true if the two registers are equal or alias
295 /// each other. The registers may be virtual register.
296 bool regsOverlap(unsigned regA, unsigned regB) const {
300 if (isVirtualRegister(regA) || isVirtualRegister(regB))
302 return areAliases(regA, regB);
305 /// getCalleeSavedRegs - Return a null-terminated list of all of the
306 /// callee saved registers on this target. The register should be in the
307 /// order of desired callee-save stack frame offset. The first register is
308 /// closed to the incoming stack pointer if stack grows down, and vice versa.
309 virtual const unsigned* getCalleeSavedRegs() const = 0;
311 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
312 /// register classes to spill each callee saved register with. The order and
313 /// length of this list match the getCalleeSaveRegs() list.
314 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
316 /// getReservedRegs - Returns a bitset indexed by physical register number
317 /// indicating if a register is a special register that has particular uses and
318 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
319 /// register scavenger to determine what registers are free.
320 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
322 //===--------------------------------------------------------------------===//
323 // Register Class Information
326 /// Register class iterators
328 regclass_iterator regclass_begin() const { return RegClassBegin; }
329 regclass_iterator regclass_end() const { return RegClassEnd; }
331 unsigned getNumRegClasses() const {
332 return regclass_end()-regclass_begin();
335 /// getRegClass - Returns the register class associated with the enumeration
336 /// value. See class TargetOperandInfo.
337 const TargetRegisterClass *getRegClass(unsigned i) const {
338 assert(i <= getNumRegClasses() && "Register Class ID out of range");
339 return i ? RegClassBegin[i - 1] : NULL;
342 //===--------------------------------------------------------------------===//
343 // Interfaces used by the register allocator and stack frame
344 // manipulation passes to move data around between registers,
345 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
348 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
349 /// registers and returns true if it isn't possible / profitable to do so by
350 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
352 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
353 MachineBasicBlock::iterator MI,
354 const std::vector<CalleeSavedInfo> &CSI) const {
358 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
359 /// saved registers and returns true if it isn't possible / profitable to do
360 /// so by issuing a series of load instructions via loadRegToStackSlot().
361 /// Returns false otherwise.
362 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
363 MachineBasicBlock::iterator MI,
364 const std::vector<CalleeSavedInfo> &CSI) const {
368 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
369 MachineBasicBlock::iterator MI,
370 unsigned SrcReg, int FrameIndex,
371 const TargetRegisterClass *RC) const = 0;
373 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
374 MachineBasicBlock::iterator MI,
375 unsigned DestReg, int FrameIndex,
376 const TargetRegisterClass *RC) const = 0;
378 virtual void copyRegToReg(MachineBasicBlock &MBB,
379 MachineBasicBlock::iterator MI,
380 unsigned DestReg, unsigned SrcReg,
381 const TargetRegisterClass *RC) const = 0;
383 /// foldMemoryOperand - Attempt to fold a load or store of the
384 /// specified stack slot into the specified machine instruction for
385 /// the specified operand. If this is possible, a new instruction
386 /// is returned with the specified operand folded, otherwise NULL is
387 /// returned. The client is responsible for removing the old
388 /// instruction and adding the new one in the instruction stream
389 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
391 int FrameIndex) const {
395 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
396 /// for rounding up the stack frame (probably at emitPrologue time).
397 virtual bool targetHandlesStackFrameRounding() const {
401 /// hasFP - Return true if the specified function should have a dedicated frame
402 /// pointer register. For most targets this is true only if the function has
403 /// variable sized allocas or if frame pointer elimination is disabled.
404 virtual bool hasFP(const MachineFunction &MF) const = 0;
406 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
407 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
408 /// targets use pseudo instructions in order to abstract away the difference
409 /// between operating with a frame pointer and operating without, through the
410 /// use of these two instructions.
412 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
413 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
416 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
417 /// code insertion to eliminate call frame setup and destroy pseudo
418 /// instructions (but only if the Target is using them). It is responsible
419 /// for eliminating these instructions, replacing them with concrete
420 /// instructions. This method need only be implemented if using call frame
421 /// setup/destroy pseudo instructions.
424 eliminateCallFramePseudoInstr(MachineFunction &MF,
425 MachineBasicBlock &MBB,
426 MachineBasicBlock::iterator MI) const {
427 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
428 "eliminateCallFramePseudoInstr must be implemented if using"
429 " call frame setup/destroy pseudo instructions!");
430 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
433 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
434 /// before PrologEpilogInserter scans the physical registers used to determine
435 /// what callee saved registers should be spilled. This method is optional.
436 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
439 /// processFunctionBeforeFrameFinalized - This method is called immediately
440 /// before the specified functions frame layout (MF.getFrameInfo()) is
441 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
442 /// replaced with direct constants. This method is optional.
444 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
447 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
448 /// frame indices from instructions which may use them. The instruction
449 /// referenced by the iterator contains an MO_FrameIndex operand which must be
450 /// eliminated by this method. This method may modify or replace the
451 /// specified instruction, as long as it keeps the iterator pointing the the
452 /// finished product. The return value is the number of instructions
453 /// added to (negative if removed from) the basic block.
455 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
457 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
458 /// the function. The return value is the number of instructions
459 /// added to (negative if removed from) the basic block (entry for prologue).
461 virtual void emitPrologue(MachineFunction &MF) const = 0;
462 virtual void emitEpilogue(MachineFunction &MF,
463 MachineBasicBlock &MBB) const = 0;
465 //===--------------------------------------------------------------------===//
466 /// Debug information queries.
468 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
469 /// number. Returns -1 if there is no equivalent value.
470 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
472 /// getFrameRegister - This method should return the register used as a base
473 /// for values allocated in the current stack frame.
474 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
476 /// getRARegister - This method should return the register where the return
477 /// address can be found.
478 virtual unsigned getRARegister() const = 0;
480 /// getLocation - This method should return the actual location of a frame
481 /// variable given the frame index. The location is returned in ML.
482 /// Subclasses should override this method for special handling of frame
483 /// variables and call MRegisterInfo::getLocation for the default action.
484 virtual void getLocation(MachineFunction &MF, unsigned Index,
485 MachineLocation &ML) const;
487 /// getInitialFrameState - Returns a list of machine moves that are assumed
488 /// on entry to all functions. Note that LabelID is ignored (assumed to be
489 /// the beginning of the function.)
490 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
493 // This is useful when building IndexedMaps keyed on virtual registers
494 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
495 unsigned operator()(unsigned Reg) const {
496 return Reg - MRegisterInfo::FirstVirtualRegister;
500 } // End llvm namespace