1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class CalleeSavedInfo;
28 class MachineFunction;
30 class MachineLocation;
33 class TargetRegisterClass;
36 /// TargetRegisterDesc - This record contains all of the information known about
37 /// a particular register. The AliasSet field (if not null) contains a pointer
38 /// to a Zero terminated array of registers that this register aliases. This is
39 /// needed for architectures like X86 which have AL alias AX alias EAX.
40 /// Registers that this does not apply to simply should set this to null.
42 struct TargetRegisterDesc {
43 const char *Name; // Assembly language name for the register
44 const unsigned *AliasSet; // Register Alias Set, described above
47 class TargetRegisterClass {
49 typedef const unsigned* iterator;
50 typedef const unsigned* const_iterator;
52 typedef const MVT::ValueType* vt_iterator;
53 typedef const TargetRegisterClass* const * sc_iterator;
57 const vt_iterator VTs;
58 const sc_iterator SubClasses;
59 const sc_iterator SuperClasses;
60 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
61 const iterator RegsBegin, RegsEnd;
63 TargetRegisterClass(unsigned id,
64 const MVT::ValueType *vts,
65 const TargetRegisterClass * const *subcs,
66 const TargetRegisterClass * const *supcs,
67 unsigned RS, unsigned Al, iterator RB, iterator RE)
68 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
69 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
70 virtual ~TargetRegisterClass() {} // Allow subclasses
72 /// getID() - Return the register class ID number.
74 unsigned getID() const { return ID; }
76 /// begin/end - Return all of the registers in this class.
78 iterator begin() const { return RegsBegin; }
79 iterator end() const { return RegsEnd; }
81 /// getNumRegs - Return the number of registers in this class.
83 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
85 /// getRegister - Return the specified register in the class.
87 unsigned getRegister(unsigned i) const {
88 assert(i < getNumRegs() && "Register number out of range!");
92 /// contains - Return true if the specified register is included in this
94 bool contains(unsigned Reg) const {
95 for (iterator I = begin(), E = end(); I != E; ++I)
96 if (*I == Reg) return true;
100 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
102 bool hasType(MVT::ValueType vt) const {
103 for(int i = 0; VTs[i] != MVT::Other; ++i)
109 /// vt_begin / vt_end - Loop over all of the value types that can be
110 /// represented by values in this register class.
111 vt_iterator vt_begin() const {
115 vt_iterator vt_end() const {
117 while (*I != MVT::Other) ++I;
121 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
122 /// sub-register class of this TargetRegisterClass.
123 bool hasSubRegClass(const TargetRegisterClass *cs) const {
124 for (int i = 0; SubClasses[i] != NULL; ++i)
125 if (SubClasses[i] == cs)
130 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
131 /// this register class.
132 sc_iterator subclasses_begin() const {
136 sc_iterator subclasses_end() const {
137 sc_iterator I = SubClasses;
138 while (*I != NULL) ++I;
142 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
143 /// super-register class of this TargetRegisterClass.
144 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
145 for (int i = 0; SuperClasses[i] != NULL; ++i)
146 if (SuperClasses[i] == cs)
151 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
152 /// of this register class.
153 sc_iterator superclasses_begin() const {
157 sc_iterator superclasses_end() const {
158 sc_iterator I = SuperClasses;
159 while (*I != NULL) ++I;
163 /// allocation_order_begin/end - These methods define a range of registers
164 /// which specify the registers in this class that are valid to register
165 /// allocate, and the preferred order to allocate them in. For example,
166 /// callee saved registers should be at the end of the list, because it is
167 /// cheaper to allocate caller saved registers.
169 /// These methods take a MachineFunction argument, which can be used to tune
170 /// the allocatable registers based on the characteristics of the function.
171 /// One simple example is that the frame pointer register can be used if
172 /// frame-pointer-elimination is performed.
174 /// By default, these methods return all registers in the class.
176 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
179 virtual iterator allocation_order_end(const MachineFunction &MF) const {
185 /// getSize - Return the size of the register in bytes, which is also the size
186 /// of a stack slot allocated to hold a spilled copy of this register.
187 unsigned getSize() const { return RegSize; }
189 /// getAlignment - Return the minimum required alignment for a register of
191 unsigned getAlignment() const { return Alignment; }
195 /// MRegisterInfo base class - We assume that the target defines a static array
196 /// of TargetRegisterDesc objects that represent all of the machine registers
197 /// that the target has. As such, we simply have to track a pointer to this
198 /// array so that we can turn register number into a register descriptor.
200 class MRegisterInfo {
202 typedef const TargetRegisterClass * const * regclass_iterator;
204 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
205 unsigned NumRegs; // Number of entries in the array
207 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
209 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
211 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
212 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
213 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
214 virtual ~MRegisterInfo();
217 enum { // Define some target independent constants
218 /// NoRegister - This physical register is not a real target register. It
219 /// is useful as a sentinal.
222 /// FirstVirtualRegister - This is the first register number that is
223 /// considered to be a 'virtual' register, which is part of the SSA
224 /// namespace. This must be the same for all targets, which means that each
225 /// target is limited to 1024 registers.
226 FirstVirtualRegister = 1024
229 /// isPhysicalRegister - Return true if the specified register number is in
230 /// the physical register namespace.
231 static bool isPhysicalRegister(unsigned Reg) {
232 assert(Reg && "this is not a register!");
233 return Reg < FirstVirtualRegister;
236 /// isVirtualRegister - Return true if the specified register number is in
237 /// the virtual register namespace.
238 static bool isVirtualRegister(unsigned Reg) {
239 assert(Reg && "this is not a register!");
240 return Reg >= FirstVirtualRegister;
243 /// getAllocatableSet - Returns a bitset indexed by register number
244 /// indicating if a register is allocatable or not.
245 BitVector getAllocatableSet(MachineFunction &MF) const;
247 const TargetRegisterDesc &operator[](unsigned RegNo) const {
248 assert(RegNo < NumRegs &&
249 "Attempting to access record for invalid register number!");
253 /// Provide a get method, equivalent to [], but more useful if we have a
254 /// pointer to this object.
256 const TargetRegisterDesc &get(unsigned RegNo) const {
257 return operator[](RegNo);
260 /// getAliasSet - Return the set of registers aliased by the specified
261 /// register, or a null list of there are none. The list returned is zero
264 const unsigned *getAliasSet(unsigned RegNo) const {
265 return get(RegNo).AliasSet;
268 /// getName - Return the symbolic target specific name for the specified
269 /// physical register.
270 const char *getName(unsigned RegNo) const {
271 return get(RegNo).Name;
274 /// getNumRegs - Return the number of registers this target has
275 /// (useful for sizing arrays holding per register information)
276 unsigned getNumRegs() const {
280 /// areAliases - Returns true if the two registers alias each other,
282 bool areAliases(unsigned regA, unsigned regB) const {
283 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
284 if (*Alias == regB) return true;
288 /// regsOverlap - Returns true if the two registers are equal or alias
289 /// each other. The registers may be virtual register.
290 bool regsOverlap(unsigned regA, unsigned regB) const {
294 if (isVirtualRegister(regA) || isVirtualRegister(regB))
296 return areAliases(regA, regB);
299 /// getCalleeSavedRegs - Return a null-terminated list of all of the
300 /// callee saved registers on this target. The register should be in the
301 /// order of desired callee-save stack frame offset. The first register is
302 /// closed to the incoming stack pointer if stack grows down, and vice versa.
303 virtual const unsigned* getCalleeSavedRegs() const = 0;
305 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
306 /// register classes to spill each callee saved register with. The order and
307 /// length of this list match the getCalleeSaveRegs() list.
308 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
310 /// getReservedRegs - Returns a bitset indexed by physical register number
311 /// indicating if a register is a special register that has particular uses and
312 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
313 /// register scavenger to determine what registers are free.
314 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
316 //===--------------------------------------------------------------------===//
317 // Register Class Information
320 /// Register class iterators
322 regclass_iterator regclass_begin() const { return RegClassBegin; }
323 regclass_iterator regclass_end() const { return RegClassEnd; }
325 unsigned getNumRegClasses() const {
326 return regclass_end()-regclass_begin();
329 /// getRegClass - Returns the register class associated with the enumeration
330 /// value. See class TargetOperandInfo.
331 const TargetRegisterClass *getRegClass(unsigned i) const {
332 assert(i <= getNumRegClasses() && "Register Class ID out of range");
333 return i ? RegClassBegin[i - 1] : NULL;
336 //===--------------------------------------------------------------------===//
337 // Interfaces used by the register allocator and stack frame
338 // manipulation passes to move data around between registers,
339 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
342 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
343 /// registers and returns true if it isn't possible / profitable to do so by
344 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
346 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
347 MachineBasicBlock::iterator MI,
348 const std::vector<CalleeSavedInfo> &CSI) const {
352 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
353 /// saved registers and returns true if it isn't possible / profitable to do
354 /// so by issuing a series of load instructions via loadRegToStackSlot().
355 /// Returns false otherwise.
356 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
357 MachineBasicBlock::iterator MI,
358 const std::vector<CalleeSavedInfo> &CSI) const {
362 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
363 MachineBasicBlock::iterator MI,
364 unsigned SrcReg, int FrameIndex,
365 const TargetRegisterClass *RC) const = 0;
367 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
368 MachineBasicBlock::iterator MI,
369 unsigned DestReg, int FrameIndex,
370 const TargetRegisterClass *RC) const = 0;
372 virtual void copyRegToReg(MachineBasicBlock &MBB,
373 MachineBasicBlock::iterator MI,
374 unsigned DestReg, unsigned SrcReg,
375 const TargetRegisterClass *RC) const = 0;
377 /// foldMemoryOperand - Attempt to fold a load or store of the
378 /// specified stack slot into the specified machine instruction for
379 /// the specified operand. If this is possible, a new instruction
380 /// is returned with the specified operand folded, otherwise NULL is
381 /// returned. The client is responsible for removing the old
382 /// instruction and adding the new one in the instruction stream
383 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
385 int FrameIndex) const {
389 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
390 /// for rounding up the stack frame (probably at emitPrologue time).
391 virtual bool targetHandlesStackFrameRounding() const {
395 /// requiresRegisterScavenging - returns true if the target requires (and
396 /// can make use of) the register scavenger.
397 virtual bool requiresRegisterScavenging() const {
401 /// hasFP - Return true if the specified function should have a dedicated frame
402 /// pointer register. For most targets this is true only if the function has
403 /// variable sized allocas or if frame pointer elimination is disabled.
404 virtual bool hasFP(const MachineFunction &MF) const = 0;
406 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
407 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
408 /// targets use pseudo instructions in order to abstract away the difference
409 /// between operating with a frame pointer and operating without, through the
410 /// use of these two instructions.
412 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
413 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
416 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
417 /// code insertion to eliminate call frame setup and destroy pseudo
418 /// instructions (but only if the Target is using them). It is responsible
419 /// for eliminating these instructions, replacing them with concrete
420 /// instructions. This method need only be implemented if using call frame
421 /// setup/destroy pseudo instructions.
424 eliminateCallFramePseudoInstr(MachineFunction &MF,
425 MachineBasicBlock &MBB,
426 MachineBasicBlock::iterator MI) const {
427 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
428 "eliminateCallFramePseudoInstr must be implemented if using"
429 " call frame setup/destroy pseudo instructions!");
430 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
433 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
434 /// before PrologEpilogInserter scans the physical registers used to determine
435 /// what callee saved registers should be spilled. This method is optional.
436 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
439 /// processFunctionBeforeFrameFinalized - This method is called immediately
440 /// before the specified functions frame layout (MF.getFrameInfo()) is
441 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
442 /// replaced with direct constants. This method is optional.
444 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
447 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
448 /// frame indices from instructions which may use them. The instruction
449 /// referenced by the iterator contains an MO_FrameIndex operand which must be
450 /// eliminated by this method. This method may modify or replace the
451 /// specified instruction, as long as it keeps the iterator pointing the the
452 /// finished product. The return value is the number of instructions
453 /// added to (negative if removed from) the basic block.
455 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
456 RegScavenger *RS = NULL) const = 0;
458 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
459 /// the function. The return value is the number of instructions
460 /// added to (negative if removed from) the basic block (entry for prologue).
462 virtual void emitPrologue(MachineFunction &MF) const = 0;
463 virtual void emitEpilogue(MachineFunction &MF,
464 MachineBasicBlock &MBB) const = 0;
466 //===--------------------------------------------------------------------===//
467 /// Debug information queries.
469 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
470 /// number. Returns -1 if there is no equivalent value.
471 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
473 /// getFrameRegister - This method should return the register used as a base
474 /// for values allocated in the current stack frame.
475 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
477 /// getRARegister - This method should return the register where the return
478 /// address can be found.
479 virtual unsigned getRARegister() const = 0;
481 /// getLocation - This method should return the actual location of a frame
482 /// variable given the frame index. The location is returned in ML.
483 /// Subclasses should override this method for special handling of frame
484 /// variables and call MRegisterInfo::getLocation for the default action.
485 virtual void getLocation(MachineFunction &MF, unsigned Index,
486 MachineLocation &ML) const;
488 /// getInitialFrameState - Returns a list of machine moves that are assumed
489 /// on entry to all functions. Note that LabelID is ignored (assumed to be
490 /// the beginning of the function.)
491 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
494 // This is useful when building IndexedMaps keyed on virtual registers
495 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
496 unsigned operator()(unsigned Reg) const {
497 return Reg - MRegisterInfo::FirstVirtualRegister;
501 } // End llvm namespace