1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class MachineLocation;
31 class TargetRegisterClass;
33 /// TargetRegisterDesc - This record contains all of the information known about
34 /// a particular register. The AliasSet field (if not null) contains a pointer
35 /// to a Zero terminated array of registers that this register aliases. This is
36 /// needed for architectures like X86 which have AL alias AX alias EAX.
37 /// Registers that this does not apply to simply should set this to null.
39 struct TargetRegisterDesc {
40 const char *Name; // Assembly language name for the register
41 const unsigned *AliasSet; // Register Alias Set, described above
44 class TargetRegisterClass {
46 typedef const unsigned* iterator;
47 typedef const unsigned* const_iterator;
49 typedef const MVT::ValueType* vt_iterator;
50 typedef const TargetRegisterClass* const * sc_iterator;
53 const vt_iterator VTs;
54 const sc_iterator SubClasses;
55 const sc_iterator SuperClasses;
56 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
57 const iterator RegsBegin, RegsEnd;
59 TargetRegisterClass(const MVT::ValueType *vts,
60 const TargetRegisterClass * const *subcs,
61 const TargetRegisterClass * const *supcs,
62 unsigned RS, unsigned Al, iterator RB, iterator RE)
63 : VTs(vts), SubClasses(subcs), SuperClasses(supcs),
64 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
65 virtual ~TargetRegisterClass() {} // Allow subclasses
67 // begin/end - Return all of the registers in this class.
68 iterator begin() const { return RegsBegin; }
69 iterator end() const { return RegsEnd; }
71 // getNumRegs - Return the number of registers in this class
72 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
74 // getRegister - Return the specified register in the class
75 unsigned getRegister(unsigned i) const {
76 assert(i < getNumRegs() && "Register number out of range!");
80 /// contains - Return true if the specified register is included in this
82 bool contains(unsigned Reg) const {
83 for (iterator I = begin(), E = end(); I != E; ++I)
84 if (*I == Reg) return true;
88 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
90 bool hasType(MVT::ValueType vt) const {
91 for(int i = 0; VTs[i] != MVT::Other; ++i)
97 /// vt_begin / vt_end - Loop over all of the value types that can be
98 /// represented by values in this register class.
99 vt_iterator vt_begin() const {
103 vt_iterator vt_end() const {
105 while (*I != MVT::Other) ++I;
109 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
110 /// sub-register class of this TargetRegisterClass.
111 bool hasSubRegClass(const TargetRegisterClass *cs) const {
112 for (int i = 0; SubClasses[i] != NULL; ++i)
113 if (SubClasses[i] == cs)
118 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
119 /// this register class.
120 sc_iterator subclasses_begin() const {
124 sc_iterator subclasses_end() const {
125 sc_iterator I = SubClasses;
126 while (*I != NULL) ++I;
130 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
131 /// super-register class of this TargetRegisterClass.
132 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
133 for (int i = 0; SuperClasses[i] != NULL; ++i)
134 if (SuperClasses[i] == cs)
139 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
140 /// of this register class.
141 sc_iterator superclasses_begin() const {
145 sc_iterator superclasses_end() const {
146 sc_iterator I = SuperClasses;
147 while (*I != NULL) ++I;
151 /// allocation_order_begin/end - These methods define a range of registers
152 /// which specify the registers in this class that are valid to register
153 /// allocate, and the preferred order to allocate them in. For example,
154 /// callee saved registers should be at the end of the list, because it is
155 /// cheaper to allocate caller saved registers.
157 /// These methods take a MachineFunction argument, which can be used to tune
158 /// the allocatable registers based on the characteristics of the function.
159 /// One simple example is that the frame pointer register can be used if
160 /// frame-pointer-elimination is performed.
162 /// By default, these methods return all registers in the class.
164 virtual iterator allocation_order_begin(MachineFunction &MF) const {
167 virtual iterator allocation_order_end(MachineFunction &MF) const {
173 /// getSize - Return the size of the register in bytes, which is also the size
174 /// of a stack slot allocated to hold a spilled copy of this register.
175 unsigned getSize() const { return RegSize; }
177 /// getAlignment - Return the minimum required alignment for a register of
179 unsigned getAlignment() const { return Alignment; }
183 /// MRegisterInfo base class - We assume that the target defines a static array
184 /// of TargetRegisterDesc objects that represent all of the machine registers
185 /// that the target has. As such, we simply have to track a pointer to this
186 /// array so that we can turn register number into a register descriptor.
188 class MRegisterInfo {
190 typedef const TargetRegisterClass * const * regclass_iterator;
192 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
193 unsigned NumRegs; // Number of entries in the array
195 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
197 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
199 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
200 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
201 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
202 virtual ~MRegisterInfo();
205 enum { // Define some target independent constants
206 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
207 /// This is used as the destination register for instructions that do not
208 /// produce a value. Some frontends may use this as an operand register to
209 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
210 /// which always PRODUCES the value 0. The X86 backend does not use this
211 /// value as an operand register, except for memory references.
215 /// FirstVirtualRegister - This is the first register number that is
216 /// considered to be a 'virtual' register, which is part of the SSA
217 /// namespace. This must be the same for all targets, which means that each
218 /// target is limited to 1024 registers.
220 FirstVirtualRegister = 1024
223 /// isPhysicalRegister - Return true if the specified register number is in
224 /// the physical register namespace.
225 static bool isPhysicalRegister(unsigned Reg) {
226 assert(Reg && "this is not a register!");
227 return Reg < FirstVirtualRegister;
230 /// isVirtualRegister - Return true if the specified register number is in
231 /// the virtual register namespace.
232 static bool isVirtualRegister(unsigned Reg) {
233 assert(Reg && "this is not a register!");
234 return Reg >= FirstVirtualRegister;
237 /// getAllocatableSet - Returns a bitset indexed by register number
238 /// indicating if a register is allocatable or not.
239 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
241 const TargetRegisterDesc &operator[](unsigned RegNo) const {
242 assert(RegNo < NumRegs &&
243 "Attempting to access record for invalid register number!");
247 /// Provide a get method, equivalent to [], but more useful if we have a
248 /// pointer to this object.
250 const TargetRegisterDesc &get(unsigned RegNo) const {
251 return operator[](RegNo);
254 /// getAliasSet - Return the set of registers aliased by the specified
255 /// register, or a null list of there are none. The list returned is zero
258 const unsigned *getAliasSet(unsigned RegNo) const {
259 return get(RegNo).AliasSet;
262 /// getName - Return the symbolic target specific name for the specified
263 /// physical register.
264 const char *getName(unsigned RegNo) const {
265 return get(RegNo).Name;
268 /// getNumRegs - Return the number of registers this target has
269 /// (useful for sizing arrays holding per register information)
270 unsigned getNumRegs() const {
274 /// areAliases - Returns true if the two registers alias each other,
276 bool areAliases(unsigned regA, unsigned regB) const {
277 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
278 if (*Alias == regB) return true;
282 /// getCalleeSaveRegs - Return a null-terminated list of all of the
283 /// callee-save registers on this target.
284 virtual const unsigned* getCalleeSaveRegs() const = 0;
286 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
287 /// register classes to spill each callee-saved register with. The order and
288 /// length of this list match the getCalleeSaveRegs() list.
289 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
291 //===--------------------------------------------------------------------===//
292 // Register Class Information
295 /// Register class iterators
297 regclass_iterator regclass_begin() const { return RegClassBegin; }
298 regclass_iterator regclass_end() const { return RegClassEnd; }
300 unsigned getNumRegClasses() const {
301 return regclass_end()-regclass_begin();
304 //===--------------------------------------------------------------------===//
305 // Interfaces used by the register allocator and stack frame
306 // manipulation passes to move data around between registers,
307 // immediates and memory. The return value is the number of
308 // instructions added to (negative if removed from) the basic block.
311 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator MI,
313 unsigned SrcReg, int FrameIndex,
314 const TargetRegisterClass *RC) const = 0;
316 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
317 MachineBasicBlock::iterator MI,
318 unsigned DestReg, int FrameIndex,
319 const TargetRegisterClass *RC) const = 0;
321 virtual void copyRegToReg(MachineBasicBlock &MBB,
322 MachineBasicBlock::iterator MI,
323 unsigned DestReg, unsigned SrcReg,
324 const TargetRegisterClass *RC) const = 0;
326 /// foldMemoryOperand - Attempt to fold a load or store of the
327 /// specified stack slot into the specified machine instruction for
328 /// the specified operand. If this is possible, a new instruction
329 /// is returned with the specified operand folded, otherwise NULL is
330 /// returned. The client is responsible for removing the old
331 /// instruction and adding the new one in the instruction stream
332 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
334 int FrameIndex) const {
338 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
339 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
340 /// targets use pseudo instructions in order to abstract away the difference
341 /// between operating with a frame pointer and operating without, through the
342 /// use of these two instructions.
344 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
345 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
348 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
349 /// code insertion to eliminate call frame setup and destroy pseudo
350 /// instructions (but only if the Target is using them). It is responsible
351 /// for eliminating these instructions, replacing them with concrete
352 /// instructions. This method need only be implemented if using call frame
353 /// setup/destroy pseudo instructions.
356 eliminateCallFramePseudoInstr(MachineFunction &MF,
357 MachineBasicBlock &MBB,
358 MachineBasicBlock::iterator MI) const {
359 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
360 "eliminateCallFramePseudoInstr must be implemented if using"
361 " call frame setup/destroy pseudo instructions!");
362 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
365 /// processFunctionBeforeFrameFinalized - This method is called immediately
366 /// before the specified functions frame layout (MF.getFrameInfo()) is
367 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
368 /// replaced with direct constants. This method is optional. The return value
369 /// is the number of instructions added to (negative if removed from) the
372 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
375 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
376 /// frame indices from instructions which may use them. The instruction
377 /// referenced by the iterator contains an MO_FrameIndex operand which must be
378 /// eliminated by this method. This method may modify or replace the
379 /// specified instruction, as long as it keeps the iterator pointing the the
380 /// finished product. The return value is the number of instructions
381 /// added to (negative if removed from) the basic block.
383 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
385 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
386 /// the function. The return value is the number of instructions
387 /// added to (negative if removed from) the basic block (entry for prologue).
389 virtual void emitPrologue(MachineFunction &MF) const = 0;
390 virtual void emitEpilogue(MachineFunction &MF,
391 MachineBasicBlock &MBB) const = 0;
393 //===--------------------------------------------------------------------===//
394 /// Debug information queries.
396 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
397 /// number. Returns -1 if there is no equivalent value.
398 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
400 /// getFrameRegister - This method should return the register used as a base
401 /// for values allocated in the current stack frame.
402 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
404 /// getRARegister - This method should return the register where the return
405 /// address can be found.
406 virtual unsigned getRARegister() const = 0;
408 /// getLocation - This method should return the actual location of a frame
409 /// variable given the frame index. The location is returned in ML.
410 /// Subclasses should override this method for special handling of frame
411 /// variables and call MRegisterInfo::getLocation for the default action.
412 virtual void getLocation(MachineFunction &MF, unsigned Index,
413 MachineLocation &ML) const;
415 /// getInitialFrameState - Returns a list of machine moves that are assumed
416 /// on entry to all functions. Note that LabelID is ignored (assumed to be
417 /// the beginning of the function.)
418 virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const;
421 // This is useful when building DenseMaps keyed on virtual registers
422 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
423 unsigned operator()(unsigned Reg) const {
424 return Reg - MRegisterInfo::FirstVirtualRegister;
428 } // End llvm namespace