1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class CalleeSavedInfo;
28 class MachineFunction;
30 class MachineLocation;
33 class TargetRegisterClass;
36 /// TargetRegisterDesc - This record contains all of the information known about
37 /// a particular register. The AliasSet field (if not null) contains a pointer
38 /// to a Zero terminated array of registers that this register aliases. This is
39 /// needed for architectures like X86 which have AL alias AX alias EAX.
40 /// Registers that this does not apply to simply should set this to null.
41 /// The SubRegs field is a zero terminated array of registers that are
42 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
43 /// The SuperRegs field is a zero terminated array of registers that are
44 /// super-registers of the specific register, e.g. RAX, EAX, are sub-registers
47 struct TargetRegisterDesc {
48 const char *Name; // Assembly language name for the register
49 const unsigned *AliasSet; // Register Alias Set, described above
50 const unsigned *SubRegs; // Sub-register set, described above
51 const unsigned *SuperRegs; // Super-register set, described above
54 class TargetRegisterClass {
56 typedef const unsigned* iterator;
57 typedef const unsigned* const_iterator;
59 typedef const MVT::ValueType* vt_iterator;
60 typedef const TargetRegisterClass* const * sc_iterator;
64 const vt_iterator VTs;
65 const sc_iterator SubClasses;
66 const sc_iterator SuperClasses;
67 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
68 const iterator RegsBegin, RegsEnd;
70 TargetRegisterClass(unsigned id,
71 const MVT::ValueType *vts,
72 const TargetRegisterClass * const *subcs,
73 const TargetRegisterClass * const *supcs,
74 unsigned RS, unsigned Al, iterator RB, iterator RE)
75 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
76 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
77 virtual ~TargetRegisterClass() {} // Allow subclasses
79 /// getID() - Return the register class ID number.
81 unsigned getID() const { return ID; }
83 /// begin/end - Return all of the registers in this class.
85 iterator begin() const { return RegsBegin; }
86 iterator end() const { return RegsEnd; }
88 /// getNumRegs - Return the number of registers in this class.
90 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
92 /// getRegister - Return the specified register in the class.
94 unsigned getRegister(unsigned i) const {
95 assert(i < getNumRegs() && "Register number out of range!");
99 /// contains - Return true if the specified register is included in this
101 bool contains(unsigned Reg) const {
102 for (iterator I = begin(), E = end(); I != E; ++I)
103 if (*I == Reg) return true;
107 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
109 bool hasType(MVT::ValueType vt) const {
110 for(int i = 0; VTs[i] != MVT::Other; ++i)
116 /// vt_begin / vt_end - Loop over all of the value types that can be
117 /// represented by values in this register class.
118 vt_iterator vt_begin() const {
122 vt_iterator vt_end() const {
124 while (*I != MVT::Other) ++I;
128 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
129 /// sub-register class of this TargetRegisterClass.
130 bool hasSubRegClass(const TargetRegisterClass *cs) const {
131 for (int i = 0; SubClasses[i] != NULL; ++i)
132 if (SubClasses[i] == cs)
137 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
138 /// this register class.
139 sc_iterator subclasses_begin() const {
143 sc_iterator subclasses_end() const {
144 sc_iterator I = SubClasses;
145 while (*I != NULL) ++I;
149 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
150 /// super-register class of this TargetRegisterClass.
151 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
152 for (int i = 0; SuperClasses[i] != NULL; ++i)
153 if (SuperClasses[i] == cs)
158 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
159 /// of this register class.
160 sc_iterator superclasses_begin() const {
164 sc_iterator superclasses_end() const {
165 sc_iterator I = SuperClasses;
166 while (*I != NULL) ++I;
170 /// allocation_order_begin/end - These methods define a range of registers
171 /// which specify the registers in this class that are valid to register
172 /// allocate, and the preferred order to allocate them in. For example,
173 /// callee saved registers should be at the end of the list, because it is
174 /// cheaper to allocate caller saved registers.
176 /// These methods take a MachineFunction argument, which can be used to tune
177 /// the allocatable registers based on the characteristics of the function.
178 /// One simple example is that the frame pointer register can be used if
179 /// frame-pointer-elimination is performed.
181 /// By default, these methods return all registers in the class.
183 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
186 virtual iterator allocation_order_end(const MachineFunction &MF) const {
192 /// getSize - Return the size of the register in bytes, which is also the size
193 /// of a stack slot allocated to hold a spilled copy of this register.
194 unsigned getSize() const { return RegSize; }
196 /// getAlignment - Return the minimum required alignment for a register of
198 unsigned getAlignment() const { return Alignment; }
202 /// MRegisterInfo base class - We assume that the target defines a static array
203 /// of TargetRegisterDesc objects that represent all of the machine registers
204 /// that the target has. As such, we simply have to track a pointer to this
205 /// array so that we can turn register number into a register descriptor.
207 class MRegisterInfo {
209 typedef const TargetRegisterClass * const * regclass_iterator;
211 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
212 unsigned NumRegs; // Number of entries in the array
214 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
216 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
218 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
219 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
220 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
221 virtual ~MRegisterInfo();
224 enum { // Define some target independent constants
225 /// NoRegister - This physical register is not a real target register. It
226 /// is useful as a sentinal.
229 /// FirstVirtualRegister - This is the first register number that is
230 /// considered to be a 'virtual' register, which is part of the SSA
231 /// namespace. This must be the same for all targets, which means that each
232 /// target is limited to 1024 registers.
233 FirstVirtualRegister = 1024
236 /// isPhysicalRegister - Return true if the specified register number is in
237 /// the physical register namespace.
238 static bool isPhysicalRegister(unsigned Reg) {
239 assert(Reg && "this is not a register!");
240 return Reg < FirstVirtualRegister;
243 /// isVirtualRegister - Return true if the specified register number is in
244 /// the virtual register namespace.
245 static bool isVirtualRegister(unsigned Reg) {
246 assert(Reg && "this is not a register!");
247 return Reg >= FirstVirtualRegister;
250 /// getAllocatableSet - Returns a bitset indexed by register number
251 /// indicating if a register is allocatable or not. If a register class is
252 /// specified, returns the subset for the class.
253 BitVector getAllocatableSet(MachineFunction &MF,
254 const TargetRegisterClass *RC = NULL) const;
256 const TargetRegisterDesc &operator[](unsigned RegNo) const {
257 assert(RegNo < NumRegs &&
258 "Attempting to access record for invalid register number!");
262 /// Provide a get method, equivalent to [], but more useful if we have a
263 /// pointer to this object.
265 const TargetRegisterDesc &get(unsigned RegNo) const {
266 return operator[](RegNo);
269 /// getAliasSet - Return the set of registers aliased by the specified
270 /// register, or a null list of there are none. The list returned is zero
273 const unsigned *getAliasSet(unsigned RegNo) const {
274 return get(RegNo).AliasSet;
277 /// getSubRegisters - Return the set of registers that are sub-registers of
278 /// the specified register, or a null list of there are none. The list
279 /// returned is zero terminated.
281 const unsigned *getSubRegisters(unsigned RegNo) const {
282 return get(RegNo).SubRegs;
285 /// getSuperRegisters - Return the set of registers that are super-registers
286 /// of the specified register, or a null list of there are none. The list
287 /// returned is zero terminated.
289 const unsigned *getSuperRegisters(unsigned RegNo) const {
290 return get(RegNo).SuperRegs;
293 /// getName - Return the symbolic target specific name for the specified
294 /// physical register.
295 const char *getName(unsigned RegNo) const {
296 return get(RegNo).Name;
299 /// getNumRegs - Return the number of registers this target has
300 /// (useful for sizing arrays holding per register information)
301 unsigned getNumRegs() const {
305 /// areAliases - Returns true if the two registers alias each other,
307 bool areAliases(unsigned regA, unsigned regB) const {
308 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
309 if (*Alias == regB) return true;
313 /// regsOverlap - Returns true if the two registers are equal or alias
314 /// each other. The registers may be virtual register.
315 bool regsOverlap(unsigned regA, unsigned regB) const {
319 if (isVirtualRegister(regA) || isVirtualRegister(regB))
321 return areAliases(regA, regB);
324 /// getCalleeSavedRegs - Return a null-terminated list of all of the
325 /// callee saved registers on this target. The register should be in the
326 /// order of desired callee-save stack frame offset. The first register is
327 /// closed to the incoming stack pointer if stack grows down, and vice versa.
328 virtual const unsigned* getCalleeSavedRegs() const = 0;
330 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
331 /// register classes to spill each callee saved register with. The order and
332 /// length of this list match the getCalleeSaveRegs() list.
333 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
335 /// getReservedRegs - Returns a bitset indexed by physical register number
336 /// indicating if a register is a special register that has particular uses and
337 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
338 /// register scavenger to determine what registers are free.
339 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
341 //===--------------------------------------------------------------------===//
342 // Register Class Information
345 /// Register class iterators
347 regclass_iterator regclass_begin() const { return RegClassBegin; }
348 regclass_iterator regclass_end() const { return RegClassEnd; }
350 unsigned getNumRegClasses() const {
351 return regclass_end()-regclass_begin();
354 /// getRegClass - Returns the register class associated with the enumeration
355 /// value. See class TargetOperandInfo.
356 const TargetRegisterClass *getRegClass(unsigned i) const {
357 assert(i <= getNumRegClasses() && "Register Class ID out of range");
358 return i ? RegClassBegin[i - 1] : NULL;
361 //===--------------------------------------------------------------------===//
362 // Interfaces used by the register allocator and stack frame
363 // manipulation passes to move data around between registers,
364 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
367 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
368 /// registers and returns true if it isn't possible / profitable to do so by
369 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
371 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
372 MachineBasicBlock::iterator MI,
373 const std::vector<CalleeSavedInfo> &CSI) const {
377 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
378 /// saved registers and returns true if it isn't possible / profitable to do
379 /// so by issuing a series of load instructions via loadRegToStackSlot().
380 /// Returns false otherwise.
381 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
382 MachineBasicBlock::iterator MI,
383 const std::vector<CalleeSavedInfo> &CSI) const {
387 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
388 MachineBasicBlock::iterator MI,
389 unsigned SrcReg, int FrameIndex,
390 const TargetRegisterClass *RC) const = 0;
392 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator MI,
394 unsigned DestReg, int FrameIndex,
395 const TargetRegisterClass *RC) const = 0;
397 virtual void copyRegToReg(MachineBasicBlock &MBB,
398 MachineBasicBlock::iterator MI,
399 unsigned DestReg, unsigned SrcReg,
400 const TargetRegisterClass *RC) const = 0;
402 /// reMaterialize - Re-issue the specified 'original' instruction at the
403 /// specific location targeting a new destination register.
404 virtual void reMaterialize(MachineBasicBlock &MBB,
405 MachineBasicBlock::iterator MI,
407 const MachineInstr *Orig) const = 0;
409 /// foldMemoryOperand - Attempt to fold a load or store of the
410 /// specified stack slot into the specified machine instruction for
411 /// the specified operand. If this is possible, a new instruction
412 /// is returned with the specified operand folded, otherwise NULL is
413 /// returned. The client is responsible for removing the old
414 /// instruction and adding the new one in the instruction stream
415 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
417 int FrameIndex) const {
421 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
422 /// for rounding up the stack frame (probably at emitPrologue time).
423 virtual bool targetHandlesStackFrameRounding() const {
427 /// requiresRegisterScavenging - returns true if the target requires (and
428 /// can make use of) the register scavenger.
429 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
433 /// hasFP - Return true if the specified function should have a dedicated frame
434 /// pointer register. For most targets this is true only if the function has
435 /// variable sized allocas or if frame pointer elimination is disabled.
436 virtual bool hasFP(const MachineFunction &MF) const = 0;
438 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
439 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
440 /// targets use pseudo instructions in order to abstract away the difference
441 /// between operating with a frame pointer and operating without, through the
442 /// use of these two instructions.
444 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
445 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
448 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
449 /// code insertion to eliminate call frame setup and destroy pseudo
450 /// instructions (but only if the Target is using them). It is responsible
451 /// for eliminating these instructions, replacing them with concrete
452 /// instructions. This method need only be implemented if using call frame
453 /// setup/destroy pseudo instructions.
456 eliminateCallFramePseudoInstr(MachineFunction &MF,
457 MachineBasicBlock &MBB,
458 MachineBasicBlock::iterator MI) const {
459 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
460 "eliminateCallFramePseudoInstr must be implemented if using"
461 " call frame setup/destroy pseudo instructions!");
462 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
465 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
466 /// before PrologEpilogInserter scans the physical registers used to determine
467 /// what callee saved registers should be spilled. This method is optional.
468 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
469 RegScavenger *RS = NULL) const {
473 /// processFunctionBeforeFrameFinalized - This method is called immediately
474 /// before the specified functions frame layout (MF.getFrameInfo()) is
475 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
476 /// replaced with direct constants. This method is optional.
478 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
481 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
482 /// frame indices from instructions which may use them. The instruction
483 /// referenced by the iterator contains an MO_FrameIndex operand which must be
484 /// eliminated by this method. This method may modify or replace the
485 /// specified instruction, as long as it keeps the iterator pointing the the
486 /// finished product. The return value is the number of instructions
487 /// added to (negative if removed from) the basic block.
489 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
490 RegScavenger *RS = NULL) const = 0;
492 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
493 /// the function. The return value is the number of instructions
494 /// added to (negative if removed from) the basic block (entry for prologue).
496 virtual void emitPrologue(MachineFunction &MF) const = 0;
497 virtual void emitEpilogue(MachineFunction &MF,
498 MachineBasicBlock &MBB) const = 0;
500 //===--------------------------------------------------------------------===//
501 /// Debug information queries.
503 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
504 /// number. Returns -1 if there is no equivalent value.
505 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
507 /// getFrameRegister - This method should return the register used as a base
508 /// for values allocated in the current stack frame.
509 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
511 /// getRARegister - This method should return the register where the return
512 /// address can be found.
513 virtual unsigned getRARegister() const = 0;
515 /// getLocation - This method should return the actual location of a frame
516 /// variable given the frame index. The location is returned in ML.
517 /// Subclasses should override this method for special handling of frame
518 /// variables and call MRegisterInfo::getLocation for the default action.
519 virtual void getLocation(MachineFunction &MF, unsigned Index,
520 MachineLocation &ML) const;
522 /// getInitialFrameState - Returns a list of machine moves that are assumed
523 /// on entry to all functions. Note that LabelID is ignored (assumed to be
524 /// the beginning of the function.)
525 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
528 // This is useful when building IndexedMaps keyed on virtual registers
529 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
530 unsigned operator()(unsigned Reg) const {
531 return Reg - MRegisterInfo::FirstVirtualRegister;
535 } // End llvm namespace