1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class MachineLocation;
31 class TargetRegisterClass;
33 /// TargetRegisterDesc - This record contains all of the information known about
34 /// a particular register. The AliasSet field (if not null) contains a pointer
35 /// to a Zero terminated array of registers that this register aliases. This is
36 /// needed for architectures like X86 which have AL alias AX alias EAX.
37 /// Registers that this does not apply to simply should set this to null.
39 struct TargetRegisterDesc {
40 const char *Name; // Assembly language name for the register
41 const unsigned *AliasSet; // Register Alias Set, described above
44 class TargetRegisterClass {
46 typedef const unsigned* iterator;
47 typedef const unsigned* const_iterator;
49 typedef const MVT::ValueType* vt_iterator;
50 typedef const TargetRegisterClass* const * sc_iterator;
54 const vt_iterator VTs;
55 const sc_iterator SubClasses;
56 const sc_iterator SuperClasses;
57 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
58 const iterator RegsBegin, RegsEnd;
60 TargetRegisterClass(unsigned id,
61 const MVT::ValueType *vts,
62 const TargetRegisterClass * const *subcs,
63 const TargetRegisterClass * const *supcs,
64 unsigned RS, unsigned Al, iterator RB, iterator RE)
65 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
66 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
67 virtual ~TargetRegisterClass() {} // Allow subclasses
69 // getID() - Return the register class ID number.
70 unsigned getID() const { return ID; }
72 // begin/end - Return all of the registers in this class.
73 iterator begin() const { return RegsBegin; }
74 iterator end() const { return RegsEnd; }
76 // getNumRegs - Return the number of registers in this class
77 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
79 // getRegister - Return the specified register in the class
80 unsigned getRegister(unsigned i) const {
81 assert(i < getNumRegs() && "Register number out of range!");
85 /// contains - Return true if the specified register is included in this
87 bool contains(unsigned Reg) const {
88 for (iterator I = begin(), E = end(); I != E; ++I)
89 if (*I == Reg) return true;
93 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
95 bool hasType(MVT::ValueType vt) const {
96 for(int i = 0; VTs[i] != MVT::Other; ++i)
102 /// vt_begin / vt_end - Loop over all of the value types that can be
103 /// represented by values in this register class.
104 vt_iterator vt_begin() const {
108 vt_iterator vt_end() const {
110 while (*I != MVT::Other) ++I;
114 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
115 /// sub-register class of this TargetRegisterClass.
116 bool hasSubRegClass(const TargetRegisterClass *cs) const {
117 for (int i = 0; SubClasses[i] != NULL; ++i)
118 if (SubClasses[i] == cs)
123 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
124 /// this register class.
125 sc_iterator subclasses_begin() const {
129 sc_iterator subclasses_end() const {
130 sc_iterator I = SubClasses;
131 while (*I != NULL) ++I;
135 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
136 /// super-register class of this TargetRegisterClass.
137 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
138 for (int i = 0; SuperClasses[i] != NULL; ++i)
139 if (SuperClasses[i] == cs)
144 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
145 /// of this register class.
146 sc_iterator superclasses_begin() const {
150 sc_iterator superclasses_end() const {
151 sc_iterator I = SuperClasses;
152 while (*I != NULL) ++I;
156 /// allocation_order_begin/end - These methods define a range of registers
157 /// which specify the registers in this class that are valid to register
158 /// allocate, and the preferred order to allocate them in. For example,
159 /// callee saved registers should be at the end of the list, because it is
160 /// cheaper to allocate caller saved registers.
162 /// These methods take a MachineFunction argument, which can be used to tune
163 /// the allocatable registers based on the characteristics of the function.
164 /// One simple example is that the frame pointer register can be used if
165 /// frame-pointer-elimination is performed.
167 /// By default, these methods return all registers in the class.
169 virtual iterator allocation_order_begin(MachineFunction &MF) const {
172 virtual iterator allocation_order_end(MachineFunction &MF) const {
178 /// getSize - Return the size of the register in bytes, which is also the size
179 /// of a stack slot allocated to hold a spilled copy of this register.
180 unsigned getSize() const { return RegSize; }
182 /// getAlignment - Return the minimum required alignment for a register of
184 unsigned getAlignment() const { return Alignment; }
188 /// MRegisterInfo base class - We assume that the target defines a static array
189 /// of TargetRegisterDesc objects that represent all of the machine registers
190 /// that the target has. As such, we simply have to track a pointer to this
191 /// array so that we can turn register number into a register descriptor.
193 class MRegisterInfo {
195 typedef const TargetRegisterClass * const * regclass_iterator;
197 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
198 unsigned NumRegs; // Number of entries in the array
200 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
202 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
204 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
205 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
206 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
207 virtual ~MRegisterInfo();
210 enum { // Define some target independent constants
211 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
212 /// This is used as the destination register for instructions that do not
213 /// produce a value. Some frontends may use this as an operand register to
214 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
215 /// which always PRODUCES the value 0. The X86 backend does not use this
216 /// value as an operand register, except for memory references.
220 /// FirstVirtualRegister - This is the first register number that is
221 /// considered to be a 'virtual' register, which is part of the SSA
222 /// namespace. This must be the same for all targets, which means that each
223 /// target is limited to 1024 registers.
225 FirstVirtualRegister = 1024
228 /// isPhysicalRegister - Return true if the specified register number is in
229 /// the physical register namespace.
230 static bool isPhysicalRegister(unsigned Reg) {
231 assert(Reg && "this is not a register!");
232 return Reg < FirstVirtualRegister;
235 /// isVirtualRegister - Return true if the specified register number is in
236 /// the virtual register namespace.
237 static bool isVirtualRegister(unsigned Reg) {
238 assert(Reg && "this is not a register!");
239 return Reg >= FirstVirtualRegister;
242 /// getAllocatableSet - Returns a bitset indexed by register number
243 /// indicating if a register is allocatable or not.
244 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
246 const TargetRegisterDesc &operator[](unsigned RegNo) const {
247 assert(RegNo < NumRegs &&
248 "Attempting to access record for invalid register number!");
252 /// Provide a get method, equivalent to [], but more useful if we have a
253 /// pointer to this object.
255 const TargetRegisterDesc &get(unsigned RegNo) const {
256 return operator[](RegNo);
259 /// getAliasSet - Return the set of registers aliased by the specified
260 /// register, or a null list of there are none. The list returned is zero
263 const unsigned *getAliasSet(unsigned RegNo) const {
264 return get(RegNo).AliasSet;
267 /// getName - Return the symbolic target specific name for the specified
268 /// physical register.
269 const char *getName(unsigned RegNo) const {
270 return get(RegNo).Name;
273 /// getNumRegs - Return the number of registers this target has
274 /// (useful for sizing arrays holding per register information)
275 unsigned getNumRegs() const {
279 /// areAliases - Returns true if the two registers alias each other,
281 bool areAliases(unsigned regA, unsigned regB) const {
282 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
283 if (*Alias == regB) return true;
287 /// getCalleeSaveRegs - Return a null-terminated list of all of the
288 /// callee-save registers on this target.
289 virtual const unsigned* getCalleeSaveRegs() const = 0;
291 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
292 /// register classes to spill each callee-saved register with. The order and
293 /// length of this list match the getCalleeSaveRegs() list.
294 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
296 //===--------------------------------------------------------------------===//
297 // Register Class Information
300 /// Register class iterators
302 regclass_iterator regclass_begin() const { return RegClassBegin; }
303 regclass_iterator regclass_end() const { return RegClassEnd; }
305 unsigned getNumRegClasses() const {
306 return regclass_end()-regclass_begin();
309 /// getRegClass - Returns the register class associated with the enumeration
310 /// value. See class TargetOperandInfo.
311 const TargetRegisterClass *getRegClass(unsigned i) const {
312 assert(i <= getNumRegClasses() && "Register Class ID out of range");
313 return i ? RegClassBegin[i - 1] : NULL;
316 //===--------------------------------------------------------------------===//
317 // Interfaces used by the register allocator and stack frame
318 // manipulation passes to move data around between registers,
319 // immediates and memory. The return value is the number of
320 // instructions added to (negative if removed from) the basic block.
323 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
324 MachineBasicBlock::iterator MI,
325 unsigned SrcReg, int FrameIndex,
326 const TargetRegisterClass *RC) const = 0;
328 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
329 MachineBasicBlock::iterator MI,
330 unsigned DestReg, int FrameIndex,
331 const TargetRegisterClass *RC) const = 0;
333 virtual void copyRegToReg(MachineBasicBlock &MBB,
334 MachineBasicBlock::iterator MI,
335 unsigned DestReg, unsigned SrcReg,
336 const TargetRegisterClass *RC) const = 0;
338 /// foldMemoryOperand - Attempt to fold a load or store of the
339 /// specified stack slot into the specified machine instruction for
340 /// the specified operand. If this is possible, a new instruction
341 /// is returned with the specified operand folded, otherwise NULL is
342 /// returned. The client is responsible for removing the old
343 /// instruction and adding the new one in the instruction stream
344 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
346 int FrameIndex) const {
350 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
351 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
352 /// targets use pseudo instructions in order to abstract away the difference
353 /// between operating with a frame pointer and operating without, through the
354 /// use of these two instructions.
356 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
357 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
360 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
361 /// code insertion to eliminate call frame setup and destroy pseudo
362 /// instructions (but only if the Target is using them). It is responsible
363 /// for eliminating these instructions, replacing them with concrete
364 /// instructions. This method need only be implemented if using call frame
365 /// setup/destroy pseudo instructions.
368 eliminateCallFramePseudoInstr(MachineFunction &MF,
369 MachineBasicBlock &MBB,
370 MachineBasicBlock::iterator MI) const {
371 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
372 "eliminateCallFramePseudoInstr must be implemented if using"
373 " call frame setup/destroy pseudo instructions!");
374 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
377 /// processFunctionBeforeFrameFinalized - This method is called immediately
378 /// before the specified functions frame layout (MF.getFrameInfo()) is
379 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
380 /// replaced with direct constants. This method is optional. The return value
381 /// is the number of instructions added to (negative if removed from) the
384 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
387 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
388 /// frame indices from instructions which may use them. The instruction
389 /// referenced by the iterator contains an MO_FrameIndex operand which must be
390 /// eliminated by this method. This method may modify or replace the
391 /// specified instruction, as long as it keeps the iterator pointing the the
392 /// finished product. The return value is the number of instructions
393 /// added to (negative if removed from) the basic block.
395 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
397 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
398 /// the function. The return value is the number of instructions
399 /// added to (negative if removed from) the basic block (entry for prologue).
401 virtual void emitPrologue(MachineFunction &MF) const = 0;
402 virtual void emitEpilogue(MachineFunction &MF,
403 MachineBasicBlock &MBB) const = 0;
405 //===--------------------------------------------------------------------===//
406 /// Debug information queries.
408 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
409 /// number. Returns -1 if there is no equivalent value.
410 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
412 /// getFrameRegister - This method should return the register used as a base
413 /// for values allocated in the current stack frame.
414 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
416 /// getRARegister - This method should return the register where the return
417 /// address can be found.
418 virtual unsigned getRARegister() const = 0;
420 /// getLocation - This method should return the actual location of a frame
421 /// variable given the frame index. The location is returned in ML.
422 /// Subclasses should override this method for special handling of frame
423 /// variables and call MRegisterInfo::getLocation for the default action.
424 virtual void getLocation(MachineFunction &MF, unsigned Index,
425 MachineLocation &ML) const;
427 /// getInitialFrameState - Returns a list of machine moves that are assumed
428 /// on entry to all functions. Note that LabelID is ignored (assumed to be
429 /// the beginning of the function.)
430 virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const;
433 // This is useful when building DenseMaps keyed on virtual registers
434 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
435 unsigned operator()(unsigned Reg) const {
436 return Reg - MRegisterInfo::FirstVirtualRegister;
440 } // End llvm namespace