1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class MachineLocation;
31 class TargetRegisterClass;
32 class CalleeSavedInfo;
35 /// TargetRegisterDesc - This record contains all of the information known about
36 /// a particular register. The AliasSet field (if not null) contains a pointer
37 /// to a Zero terminated array of registers that this register aliases. This is
38 /// needed for architectures like X86 which have AL alias AX alias EAX.
39 /// Registers that this does not apply to simply should set this to null.
41 struct TargetRegisterDesc {
42 const char *Name; // Assembly language name for the register
43 const unsigned *AliasSet; // Register Alias Set, described above
46 class TargetRegisterClass {
48 typedef const unsigned* iterator;
49 typedef const unsigned* const_iterator;
51 typedef const MVT::ValueType* vt_iterator;
52 typedef const TargetRegisterClass* const * sc_iterator;
56 const vt_iterator VTs;
57 const sc_iterator SubClasses;
58 const sc_iterator SuperClasses;
59 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
60 const iterator RegsBegin, RegsEnd;
62 TargetRegisterClass(unsigned id,
63 const MVT::ValueType *vts,
64 const TargetRegisterClass * const *subcs,
65 const TargetRegisterClass * const *supcs,
66 unsigned RS, unsigned Al, iterator RB, iterator RE)
67 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
68 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
69 virtual ~TargetRegisterClass() {} // Allow subclasses
71 /// getID() - Return the register class ID number.
73 unsigned getID() const { return ID; }
75 /// begin/end - Return all of the registers in this class.
77 iterator begin() const { return RegsBegin; }
78 iterator end() const { return RegsEnd; }
80 /// getNumRegs - Return the number of registers in this class.
82 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
84 /// getRegister - Return the specified register in the class.
86 unsigned getRegister(unsigned i) const {
87 assert(i < getNumRegs() && "Register number out of range!");
91 /// contains - Return true if the specified register is included in this
93 bool contains(unsigned Reg) const {
94 for (iterator I = begin(), E = end(); I != E; ++I)
95 if (*I == Reg) return true;
99 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
101 bool hasType(MVT::ValueType vt) const {
102 for(int i = 0; VTs[i] != MVT::Other; ++i)
108 /// vt_begin / vt_end - Loop over all of the value types that can be
109 /// represented by values in this register class.
110 vt_iterator vt_begin() const {
114 vt_iterator vt_end() const {
116 while (*I != MVT::Other) ++I;
120 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
121 /// sub-register class of this TargetRegisterClass.
122 bool hasSubRegClass(const TargetRegisterClass *cs) const {
123 for (int i = 0; SubClasses[i] != NULL; ++i)
124 if (SubClasses[i] == cs)
129 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
130 /// this register class.
131 sc_iterator subclasses_begin() const {
135 sc_iterator subclasses_end() const {
136 sc_iterator I = SubClasses;
137 while (*I != NULL) ++I;
141 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
142 /// super-register class of this TargetRegisterClass.
143 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
144 for (int i = 0; SuperClasses[i] != NULL; ++i)
145 if (SuperClasses[i] == cs)
150 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
151 /// of this register class.
152 sc_iterator superclasses_begin() const {
156 sc_iterator superclasses_end() const {
157 sc_iterator I = SuperClasses;
158 while (*I != NULL) ++I;
162 /// allocation_order_begin/end - These methods define a range of registers
163 /// which specify the registers in this class that are valid to register
164 /// allocate, and the preferred order to allocate them in. For example,
165 /// callee saved registers should be at the end of the list, because it is
166 /// cheaper to allocate caller saved registers.
168 /// These methods take a MachineFunction argument, which can be used to tune
169 /// the allocatable registers based on the characteristics of the function.
170 /// One simple example is that the frame pointer register can be used if
171 /// frame-pointer-elimination is performed.
173 /// By default, these methods return all registers in the class.
175 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
178 virtual iterator allocation_order_end(const MachineFunction &MF) const {
184 /// getSize - Return the size of the register in bytes, which is also the size
185 /// of a stack slot allocated to hold a spilled copy of this register.
186 unsigned getSize() const { return RegSize; }
188 /// getAlignment - Return the minimum required alignment for a register of
190 unsigned getAlignment() const { return Alignment; }
194 /// MRegisterInfo base class - We assume that the target defines a static array
195 /// of TargetRegisterDesc objects that represent all of the machine registers
196 /// that the target has. As such, we simply have to track a pointer to this
197 /// array so that we can turn register number into a register descriptor.
199 class MRegisterInfo {
201 typedef const TargetRegisterClass * const * regclass_iterator;
203 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
204 unsigned NumRegs; // Number of entries in the array
206 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
208 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
210 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
211 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
212 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
213 virtual ~MRegisterInfo();
216 enum { // Define some target independent constants
217 /// NoRegister - This physical register is not a real target register. It
218 /// is useful as a sentinal.
221 /// FirstVirtualRegister - This is the first register number that is
222 /// considered to be a 'virtual' register, which is part of the SSA
223 /// namespace. This must be the same for all targets, which means that each
224 /// target is limited to 1024 registers.
225 FirstVirtualRegister = 1024
228 /// isPhysicalRegister - Return true if the specified register number is in
229 /// the physical register namespace.
230 static bool isPhysicalRegister(unsigned Reg) {
231 assert(Reg && "this is not a register!");
232 return Reg < FirstVirtualRegister;
235 /// isVirtualRegister - Return true if the specified register number is in
236 /// the virtual register namespace.
237 static bool isVirtualRegister(unsigned Reg) {
238 assert(Reg && "this is not a register!");
239 return Reg >= FirstVirtualRegister;
242 /// getAllocatableSet - Returns a bitset indexed by register number
243 /// indicating if a register is allocatable or not.
244 BitVector getAllocatableSet(MachineFunction &MF) const;
246 const TargetRegisterDesc &operator[](unsigned RegNo) const {
247 assert(RegNo < NumRegs &&
248 "Attempting to access record for invalid register number!");
252 /// Provide a get method, equivalent to [], but more useful if we have a
253 /// pointer to this object.
255 const TargetRegisterDesc &get(unsigned RegNo) const {
256 return operator[](RegNo);
259 /// getAliasSet - Return the set of registers aliased by the specified
260 /// register, or a null list of there are none. The list returned is zero
263 const unsigned *getAliasSet(unsigned RegNo) const {
264 return get(RegNo).AliasSet;
267 /// getName - Return the symbolic target specific name for the specified
268 /// physical register.
269 const char *getName(unsigned RegNo) const {
270 return get(RegNo).Name;
273 /// getNumRegs - Return the number of registers this target has
274 /// (useful for sizing arrays holding per register information)
275 unsigned getNumRegs() const {
279 /// areAliases - Returns true if the two registers alias each other,
281 bool areAliases(unsigned regA, unsigned regB) const {
282 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
283 if (*Alias == regB) return true;
287 /// regsOverlap - Returns true if the two registers are equal or alias
288 /// each other. The registers may be virtual register.
289 bool regsOverlap(unsigned regA, unsigned regB) const {
293 if (isVirtualRegister(regA) || isVirtualRegister(regB))
295 return areAliases(regA, regB);
298 /// getCalleeSavedRegs - Return a null-terminated list of all of the
299 /// callee saved registers on this target. The register should be in the
300 /// order of desired callee-save stack frame offset. The first register is
301 /// closed to the incoming stack pointer if stack grows down, and vice versa.
302 virtual const unsigned* getCalleeSavedRegs() const = 0;
304 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
305 /// register classes to spill each callee saved register with. The order and
306 /// length of this list match the getCalleeSaveRegs() list.
307 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
309 /// getReservedRegs - Returns a bitset indexed by physical register number
310 /// indicating if a register is a special register that has particular uses and
311 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
312 /// register scavenger to determine what registers are free.
313 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
315 //===--------------------------------------------------------------------===//
316 // Register Class Information
319 /// Register class iterators
321 regclass_iterator regclass_begin() const { return RegClassBegin; }
322 regclass_iterator regclass_end() const { return RegClassEnd; }
324 unsigned getNumRegClasses() const {
325 return regclass_end()-regclass_begin();
328 /// getRegClass - Returns the register class associated with the enumeration
329 /// value. See class TargetOperandInfo.
330 const TargetRegisterClass *getRegClass(unsigned i) const {
331 assert(i <= getNumRegClasses() && "Register Class ID out of range");
332 return i ? RegClassBegin[i - 1] : NULL;
335 //===--------------------------------------------------------------------===//
336 // Interfaces used by the register allocator and stack frame
337 // manipulation passes to move data around between registers,
338 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
341 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
342 /// registers and returns true if it isn't possible / profitable to do so by
343 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
345 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
346 MachineBasicBlock::iterator MI,
347 const std::vector<CalleeSavedInfo> &CSI) const {
351 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
352 /// saved registers and returns true if it isn't possible / profitable to do
353 /// so by issuing a series of load instructions via loadRegToStackSlot().
354 /// Returns false otherwise.
355 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
356 MachineBasicBlock::iterator MI,
357 const std::vector<CalleeSavedInfo> &CSI) const {
361 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
362 MachineBasicBlock::iterator MI,
363 unsigned SrcReg, int FrameIndex,
364 const TargetRegisterClass *RC) const = 0;
366 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
367 MachineBasicBlock::iterator MI,
368 unsigned DestReg, int FrameIndex,
369 const TargetRegisterClass *RC) const = 0;
371 virtual void copyRegToReg(MachineBasicBlock &MBB,
372 MachineBasicBlock::iterator MI,
373 unsigned DestReg, unsigned SrcReg,
374 const TargetRegisterClass *RC) const = 0;
376 /// foldMemoryOperand - Attempt to fold a load or store of the
377 /// specified stack slot into the specified machine instruction for
378 /// the specified operand. If this is possible, a new instruction
379 /// is returned with the specified operand folded, otherwise NULL is
380 /// returned. The client is responsible for removing the old
381 /// instruction and adding the new one in the instruction stream
382 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
384 int FrameIndex) const {
388 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
389 /// for rounding up the stack frame (probably at emitPrologue time).
390 virtual bool targetHandlesStackFrameRounding() const {
394 /// hasFP - Return true if the specified function should have a dedicated frame
395 /// pointer register. For most targets this is true only if the function has
396 /// variable sized allocas or if frame pointer elimination is disabled.
397 virtual bool hasFP(const MachineFunction &MF) const = 0;
399 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
400 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
401 /// targets use pseudo instructions in order to abstract away the difference
402 /// between operating with a frame pointer and operating without, through the
403 /// use of these two instructions.
405 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
406 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
409 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
410 /// code insertion to eliminate call frame setup and destroy pseudo
411 /// instructions (but only if the Target is using them). It is responsible
412 /// for eliminating these instructions, replacing them with concrete
413 /// instructions. This method need only be implemented if using call frame
414 /// setup/destroy pseudo instructions.
417 eliminateCallFramePseudoInstr(MachineFunction &MF,
418 MachineBasicBlock &MBB,
419 MachineBasicBlock::iterator MI) const {
420 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
421 "eliminateCallFramePseudoInstr must be implemented if using"
422 " call frame setup/destroy pseudo instructions!");
423 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
426 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
427 /// before PrologEpilogInserter scans the physical registers used to determine
428 /// what callee saved registers should be spilled. This method is optional.
429 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
432 /// processFunctionBeforeFrameFinalized - This method is called immediately
433 /// before the specified functions frame layout (MF.getFrameInfo()) is
434 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
435 /// replaced with direct constants. This method is optional.
437 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
440 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
441 /// frame indices from instructions which may use them. The instruction
442 /// referenced by the iterator contains an MO_FrameIndex operand which must be
443 /// eliminated by this method. This method may modify or replace the
444 /// specified instruction, as long as it keeps the iterator pointing the the
445 /// finished product. The return value is the number of instructions
446 /// added to (negative if removed from) the basic block.
448 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
450 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
451 /// the function. The return value is the number of instructions
452 /// added to (negative if removed from) the basic block (entry for prologue).
454 virtual void emitPrologue(MachineFunction &MF) const = 0;
455 virtual void emitEpilogue(MachineFunction &MF,
456 MachineBasicBlock &MBB) const = 0;
458 //===--------------------------------------------------------------------===//
459 /// Debug information queries.
461 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
462 /// number. Returns -1 if there is no equivalent value.
463 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
465 /// getFrameRegister - This method should return the register used as a base
466 /// for values allocated in the current stack frame.
467 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
469 /// getRARegister - This method should return the register where the return
470 /// address can be found.
471 virtual unsigned getRARegister() const = 0;
473 /// getEHExceptionRegister - This method should return the register containing
474 /// the address of the exception info on entry to a landing pad.
475 virtual unsigned getEHExceptionRegister() const = 0;
477 /// getEHHandlerRegister - This method should return the register containing
478 /// the switch table selection on entry to an landing pad.
479 virtual unsigned getEHHandlerRegister() const = 0;
481 /// getLocation - This method should return the actual location of a frame
482 /// variable given the frame index. The location is returned in ML.
483 /// Subclasses should override this method for special handling of frame
484 /// variables and call MRegisterInfo::getLocation for the default action.
485 virtual void getLocation(MachineFunction &MF, unsigned Index,
486 MachineLocation &ML) const;
488 /// getInitialFrameState - Returns a list of machine moves that are assumed
489 /// on entry to all functions. Note that LabelID is ignored (assumed to be
490 /// the beginning of the function.)
491 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
494 // This is useful when building IndexedMaps keyed on virtual registers
495 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
496 unsigned operator()(unsigned Reg) const {
497 return Reg - MRegisterInfo::FirstVirtualRegister;
501 } // End llvm namespace