1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class TargetRegisterClass;
31 /// TargetRegisterDesc - This record contains all of the information known about
32 /// a particular register. The AliasSet field (if not null) contains a pointer
33 /// to a Zero terminated array of registers that this register aliases. This is
34 /// needed for architectures like X86 which have AL alias AX alias EAX.
35 /// Registers that this does not apply to simply should set this to null.
37 struct TargetRegisterDesc {
38 const char *Name; // Assembly language name for the register
39 const unsigned *AliasSet; // Register Alias Set, described above
42 class TargetRegisterClass {
44 typedef const unsigned* iterator;
45 typedef const unsigned* const_iterator;
48 const MVT::ValueType* VTs;
49 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
50 const iterator RegsBegin, RegsEnd;
52 TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al,
53 iterator RB, iterator RE)
54 : VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
55 virtual ~TargetRegisterClass() {} // Allow subclasses
57 // begin/end - Return all of the registers in this class.
58 iterator begin() const { return RegsBegin; }
59 iterator end() const { return RegsEnd; }
61 // getNumRegs - Return the number of registers in this class
62 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
64 // getRegister - Return the specified register in the class
65 unsigned getRegister(unsigned i) const {
66 assert(i < getNumRegs() && "Register number out of range!");
70 /// contains - Return true if the specified register is included in this
72 bool contains(unsigned Reg) const {
73 for (iterator I = begin(), E = end(); I != E; ++I)
74 if (*I == Reg) return true;
78 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
80 bool hasType(MVT::ValueType vt) const {
81 for(int i = 0; VTs[i] != MVT::Other; ++i)
87 /// allocation_order_begin/end - These methods define a range of registers
88 /// which specify the registers in this class that are valid to register
89 /// allocate, and the preferred order to allocate them in. For example,
90 /// callee saved registers should be at the end of the list, because it is
91 /// cheaper to allocate caller saved registers.
93 /// These methods take a MachineFunction argument, which can be used to tune
94 /// the allocatable registers based on the characteristics of the function.
95 /// One simple example is that the frame pointer register can be used if
96 /// frame-pointer-elimination is performed.
98 /// By default, these methods return all registers in the class.
100 virtual iterator allocation_order_begin(MachineFunction &MF) const {
103 virtual iterator allocation_order_end(MachineFunction &MF) const {
109 /// getSize - Return the size of the register in bytes, which is also the size
110 /// of a stack slot allocated to hold a spilled copy of this register.
111 unsigned getSize() const { return RegSize; }
113 /// getAlignment - Return the minimum required alignment for a register of
115 unsigned getAlignment() const { return Alignment; }
119 /// MRegisterInfo base class - We assume that the target defines a static array
120 /// of TargetRegisterDesc objects that represent all of the machine registers
121 /// that the target has. As such, we simply have to track a pointer to this
122 /// array so that we can turn register number into a register descriptor.
124 class MRegisterInfo {
126 typedef const TargetRegisterClass * const * regclass_iterator;
128 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
129 unsigned NumRegs; // Number of entries in the array
131 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
133 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
135 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
136 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
137 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
138 virtual ~MRegisterInfo();
141 enum { // Define some target independent constants
142 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
143 /// This is used as the destination register for instructions that do not
144 /// produce a value. Some frontends may use this as an operand register to
145 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
146 /// which always PRODUCES the value 0. The X86 backend does not use this
147 /// value as an operand register, except for memory references.
151 /// FirstVirtualRegister - This is the first register number that is
152 /// considered to be a 'virtual' register, which is part of the SSA
153 /// namespace. This must be the same for all targets, which means that each
154 /// target is limited to 1024 registers.
156 FirstVirtualRegister = 1024,
159 /// isPhysicalRegister - Return true if the specified register number is in
160 /// the physical register namespace.
161 static bool isPhysicalRegister(unsigned Reg) {
162 assert(Reg && "this is not a register!");
163 return Reg < FirstVirtualRegister;
166 /// isVirtualRegister - Return true if the specified register number is in
167 /// the virtual register namespace.
168 static bool isVirtualRegister(unsigned Reg) {
169 assert(Reg && "this is not a register!");
170 return Reg >= FirstVirtualRegister;
173 /// getAllocatableSet - Returns a bitset indexed by register number
174 /// indicating if a register is allocatable or not.
175 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
177 const TargetRegisterDesc &operator[](unsigned RegNo) const {
178 assert(RegNo < NumRegs &&
179 "Attempting to access record for invalid register number!");
183 /// Provide a get method, equivalent to [], but more useful if we have a
184 /// pointer to this object.
186 const TargetRegisterDesc &get(unsigned RegNo) const {
187 return operator[](RegNo);
190 /// getAliasSet - Return the set of registers aliased by the specified
191 /// register, or a null list of there are none. The list returned is zero
194 const unsigned *getAliasSet(unsigned RegNo) const {
195 return get(RegNo).AliasSet;
198 /// getName - Return the symbolic target specific name for the specified
199 /// physical register.
200 const char *getName(unsigned RegNo) const {
201 return get(RegNo).Name;
204 /// getNumRegs - Return the number of registers this target has
205 /// (useful for sizing arrays holding per register information)
206 unsigned getNumRegs() const {
210 /// areAliases - Returns true if the two registers alias each other,
212 bool areAliases(unsigned regA, unsigned regB) const {
213 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
214 if (*Alias == regB) return true;
218 /// getCalleeSaveRegs - Return a null-terminated list of all of the
219 /// callee-save registers on this target.
220 virtual const unsigned* getCalleeSaveRegs() const = 0;
222 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
223 /// register classes to spill each callee-saved register with. The order and
224 /// length of this list match the getCalleeSaveRegs() list.
225 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
227 //===--------------------------------------------------------------------===//
228 // Register Class Information
231 /// Register class iterators
233 regclass_iterator regclass_begin() const { return RegClassBegin; }
234 regclass_iterator regclass_end() const { return RegClassEnd; }
236 unsigned getNumRegClasses() const {
237 return regclass_end()-regclass_begin();
240 //===--------------------------------------------------------------------===//
241 // Interfaces used by the register allocator and stack frame
242 // manipulation passes to move data around between registers,
243 // immediates and memory. The return value is the number of
244 // instructions added to (negative if removed from) the basic block.
247 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
248 MachineBasicBlock::iterator MI,
249 unsigned SrcReg, int FrameIndex,
250 const TargetRegisterClass *RC) const = 0;
252 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator MI,
254 unsigned DestReg, int FrameIndex,
255 const TargetRegisterClass *RC) const = 0;
257 virtual void copyRegToReg(MachineBasicBlock &MBB,
258 MachineBasicBlock::iterator MI,
259 unsigned DestReg, unsigned SrcReg,
260 const TargetRegisterClass *RC) const = 0;
262 /// isLoadFromStackSlot - If the specified machine instruction is a direct
263 /// load from a stack slot, return the virtual or physical register number of
264 /// the destination along with the FrameIndex of the loaded stack slot. If
265 /// not, return 0. This predicate must return 0 if the instruction has
266 /// any side effects other than loading from the stack slot.
267 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
271 /// isStoreToStackSlot - If the specified machine instruction is a direct
272 /// store to a stack slot, return the virtual or physical register number of
273 /// the source reg along with the FrameIndex of the loaded stack slot. If
274 /// not, return 0. This predicate must return 0 if the instruction has
275 /// any side effects other than storing to the stack slot.
276 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
280 /// foldMemoryOperand - Attempt to fold a load or store of the
281 /// specified stack slot into the specified machine instruction for
282 /// the specified operand. If this is possible, a new instruction
283 /// is returned with the specified operand folded, otherwise NULL is
284 /// returned. The client is responsible for removing the old
285 /// instruction and adding the new one in the instruction stream
286 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
288 int FrameIndex) const {
292 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
293 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
294 /// targets use pseudo instructions in order to abstract away the difference
295 /// between operating with a frame pointer and operating without, through the
296 /// use of these two instructions.
298 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
299 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
302 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
303 /// code insertion to eliminate call frame setup and destroy pseudo
304 /// instructions (but only if the Target is using them). It is responsible
305 /// for eliminating these instructions, replacing them with concrete
306 /// instructions. This method need only be implemented if using call frame
307 /// setup/destroy pseudo instructions.
310 eliminateCallFramePseudoInstr(MachineFunction &MF,
311 MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator MI) const {
313 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
314 "eliminateCallFramePseudoInstr must be implemented if using"
315 " call frame setup/destroy pseudo instructions!");
316 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
319 /// processFunctionBeforeFrameFinalized - This method is called immediately
320 /// before the specified functions frame layout (MF.getFrameInfo()) is
321 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
322 /// replaced with direct constants. This method is optional. The return value
323 /// is the number of instructions added to (negative if removed from) the
326 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
329 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
330 /// frame indices from instructions which may use them. The instruction
331 /// referenced by the iterator contains an MO_FrameIndex operand which must be
332 /// eliminated by this method. This method may modify or replace the
333 /// specified instruction, as long as it keeps the iterator pointing the the
334 /// finished product. The return value is the number of instructions
335 /// added to (negative if removed from) the basic block.
337 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
339 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
340 /// the function. The return value is the number of instructions
341 /// added to (negative if removed from) the basic block (entry for prologue).
343 virtual void emitPrologue(MachineFunction &MF) const = 0;
344 virtual void emitEpilogue(MachineFunction &MF,
345 MachineBasicBlock &MBB) const = 0;
348 // This is useful when building DenseMaps keyed on virtual registers
349 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
350 unsigned operator()(unsigned Reg) const {
351 return Reg - MRegisterInfo::FirstVirtualRegister;
355 } // End llvm namespace