1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class MachineLocation;
31 class TargetRegisterClass;
33 /// TargetRegisterDesc - This record contains all of the information known about
34 /// a particular register. The AliasSet field (if not null) contains a pointer
35 /// to a Zero terminated array of registers that this register aliases. This is
36 /// needed for architectures like X86 which have AL alias AX alias EAX.
37 /// Registers that this does not apply to simply should set this to null.
39 struct TargetRegisterDesc {
40 const char *Name; // Assembly language name for the register
41 const unsigned *AliasSet; // Register Alias Set, described above
44 class TargetRegisterClass {
46 typedef const unsigned* iterator;
47 typedef const unsigned* const_iterator;
49 typedef const MVT::ValueType* vt_iterator;
50 typedef const TargetRegisterClass** sc_iterator;
52 const vt_iterator VTs;
53 const sc_iterator SubClasses;
54 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
55 const iterator RegsBegin, RegsEnd;
57 TargetRegisterClass(const MVT::ValueType *vts,
58 const TargetRegisterClass **scs,
59 unsigned RS, unsigned Al, iterator RB, iterator RE)
60 : VTs(vts), SubClasses(scs),
61 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
62 virtual ~TargetRegisterClass() {} // Allow subclasses
64 // begin/end - Return all of the registers in this class.
65 iterator begin() const { return RegsBegin; }
66 iterator end() const { return RegsEnd; }
68 // getNumRegs - Return the number of registers in this class
69 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
71 // getRegister - Return the specified register in the class
72 unsigned getRegister(unsigned i) const {
73 assert(i < getNumRegs() && "Register number out of range!");
77 /// contains - Return true if the specified register is included in this
79 bool contains(unsigned Reg) const {
80 for (iterator I = begin(), E = end(); I != E; ++I)
81 if (*I == Reg) return true;
85 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
87 bool hasType(MVT::ValueType vt) const {
88 for(int i = 0; VTs[i] != MVT::Other; ++i)
94 /// vt_begin / vt_end - Loop over all of the value types that can be
95 /// represented by values in this register class.
96 vt_iterator vt_begin() const {
100 vt_iterator vt_end() const {
102 while (*I != MVT::Other) ++I;
106 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
107 /// sub-register class of this TargetRegisterClass.
108 bool hasSubRegClass(const TargetRegisterClass *cs) const {
109 for (int i = 0; SubClasses[i] != NULL; ++i)
110 if (SubClasses[i] == cs)
115 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
116 /// this register class.
117 sc_iterator subclasses_begin() const {
121 sc_iterator subclasses_end() const {
122 sc_iterator I = SubClasses;
123 while (*I != NULL) ++I;
127 /// allocation_order_begin/end - These methods define a range of registers
128 /// which specify the registers in this class that are valid to register
129 /// allocate, and the preferred order to allocate them in. For example,
130 /// callee saved registers should be at the end of the list, because it is
131 /// cheaper to allocate caller saved registers.
133 /// These methods take a MachineFunction argument, which can be used to tune
134 /// the allocatable registers based on the characteristics of the function.
135 /// One simple example is that the frame pointer register can be used if
136 /// frame-pointer-elimination is performed.
138 /// By default, these methods return all registers in the class.
140 virtual iterator allocation_order_begin(MachineFunction &MF) const {
143 virtual iterator allocation_order_end(MachineFunction &MF) const {
149 /// getSize - Return the size of the register in bytes, which is also the size
150 /// of a stack slot allocated to hold a spilled copy of this register.
151 unsigned getSize() const { return RegSize; }
153 /// getAlignment - Return the minimum required alignment for a register of
155 unsigned getAlignment() const { return Alignment; }
159 /// MRegisterInfo base class - We assume that the target defines a static array
160 /// of TargetRegisterDesc objects that represent all of the machine registers
161 /// that the target has. As such, we simply have to track a pointer to this
162 /// array so that we can turn register number into a register descriptor.
164 class MRegisterInfo {
166 typedef const TargetRegisterClass * const * regclass_iterator;
168 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
169 unsigned NumRegs; // Number of entries in the array
171 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
173 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
175 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
176 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
177 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
178 virtual ~MRegisterInfo();
181 enum { // Define some target independent constants
182 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
183 /// This is used as the destination register for instructions that do not
184 /// produce a value. Some frontends may use this as an operand register to
185 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
186 /// which always PRODUCES the value 0. The X86 backend does not use this
187 /// value as an operand register, except for memory references.
191 /// FirstVirtualRegister - This is the first register number that is
192 /// considered to be a 'virtual' register, which is part of the SSA
193 /// namespace. This must be the same for all targets, which means that each
194 /// target is limited to 1024 registers.
196 FirstVirtualRegister = 1024
199 /// isPhysicalRegister - Return true if the specified register number is in
200 /// the physical register namespace.
201 static bool isPhysicalRegister(unsigned Reg) {
202 assert(Reg && "this is not a register!");
203 return Reg < FirstVirtualRegister;
206 /// isVirtualRegister - Return true if the specified register number is in
207 /// the virtual register namespace.
208 static bool isVirtualRegister(unsigned Reg) {
209 assert(Reg && "this is not a register!");
210 return Reg >= FirstVirtualRegister;
213 /// getAllocatableSet - Returns a bitset indexed by register number
214 /// indicating if a register is allocatable or not.
215 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
217 const TargetRegisterDesc &operator[](unsigned RegNo) const {
218 assert(RegNo < NumRegs &&
219 "Attempting to access record for invalid register number!");
223 /// Provide a get method, equivalent to [], but more useful if we have a
224 /// pointer to this object.
226 const TargetRegisterDesc &get(unsigned RegNo) const {
227 return operator[](RegNo);
230 /// getAliasSet - Return the set of registers aliased by the specified
231 /// register, or a null list of there are none. The list returned is zero
234 const unsigned *getAliasSet(unsigned RegNo) const {
235 return get(RegNo).AliasSet;
238 /// getName - Return the symbolic target specific name for the specified
239 /// physical register.
240 const char *getName(unsigned RegNo) const {
241 return get(RegNo).Name;
244 /// getNumRegs - Return the number of registers this target has
245 /// (useful for sizing arrays holding per register information)
246 unsigned getNumRegs() const {
250 /// areAliases - Returns true if the two registers alias each other,
252 bool areAliases(unsigned regA, unsigned regB) const {
253 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
254 if (*Alias == regB) return true;
258 /// getCalleeSaveRegs - Return a null-terminated list of all of the
259 /// callee-save registers on this target.
260 virtual const unsigned* getCalleeSaveRegs() const = 0;
262 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
263 /// register classes to spill each callee-saved register with. The order and
264 /// length of this list match the getCalleeSaveRegs() list.
265 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
267 //===--------------------------------------------------------------------===//
268 // Register Class Information
271 /// Register class iterators
273 regclass_iterator regclass_begin() const { return RegClassBegin; }
274 regclass_iterator regclass_end() const { return RegClassEnd; }
276 unsigned getNumRegClasses() const {
277 return regclass_end()-regclass_begin();
280 //===--------------------------------------------------------------------===//
281 // Interfaces used by the register allocator and stack frame
282 // manipulation passes to move data around between registers,
283 // immediates and memory. The return value is the number of
284 // instructions added to (negative if removed from) the basic block.
287 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
288 MachineBasicBlock::iterator MI,
289 unsigned SrcReg, int FrameIndex,
290 const TargetRegisterClass *RC) const = 0;
292 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
293 MachineBasicBlock::iterator MI,
294 unsigned DestReg, int FrameIndex,
295 const TargetRegisterClass *RC) const = 0;
297 virtual void copyRegToReg(MachineBasicBlock &MBB,
298 MachineBasicBlock::iterator MI,
299 unsigned DestReg, unsigned SrcReg,
300 const TargetRegisterClass *RC) const = 0;
302 /// foldMemoryOperand - Attempt to fold a load or store of the
303 /// specified stack slot into the specified machine instruction for
304 /// the specified operand. If this is possible, a new instruction
305 /// is returned with the specified operand folded, otherwise NULL is
306 /// returned. The client is responsible for removing the old
307 /// instruction and adding the new one in the instruction stream
308 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
310 int FrameIndex) const {
314 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
315 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
316 /// targets use pseudo instructions in order to abstract away the difference
317 /// between operating with a frame pointer and operating without, through the
318 /// use of these two instructions.
320 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
321 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
324 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
325 /// code insertion to eliminate call frame setup and destroy pseudo
326 /// instructions (but only if the Target is using them). It is responsible
327 /// for eliminating these instructions, replacing them with concrete
328 /// instructions. This method need only be implemented if using call frame
329 /// setup/destroy pseudo instructions.
332 eliminateCallFramePseudoInstr(MachineFunction &MF,
333 MachineBasicBlock &MBB,
334 MachineBasicBlock::iterator MI) const {
335 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
336 "eliminateCallFramePseudoInstr must be implemented if using"
337 " call frame setup/destroy pseudo instructions!");
338 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
341 /// processFunctionBeforeFrameFinalized - This method is called immediately
342 /// before the specified functions frame layout (MF.getFrameInfo()) is
343 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
344 /// replaced with direct constants. This method is optional. The return value
345 /// is the number of instructions added to (negative if removed from) the
348 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
351 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
352 /// frame indices from instructions which may use them. The instruction
353 /// referenced by the iterator contains an MO_FrameIndex operand which must be
354 /// eliminated by this method. This method may modify or replace the
355 /// specified instruction, as long as it keeps the iterator pointing the the
356 /// finished product. The return value is the number of instructions
357 /// added to (negative if removed from) the basic block.
359 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
361 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
362 /// the function. The return value is the number of instructions
363 /// added to (negative if removed from) the basic block (entry for prologue).
365 virtual void emitPrologue(MachineFunction &MF) const = 0;
366 virtual void emitEpilogue(MachineFunction &MF,
367 MachineBasicBlock &MBB) const = 0;
369 //===--------------------------------------------------------------------===//
370 /// Debug information queries.
372 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
373 /// number. Returns -1 if there is no equivalent value.
374 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
376 /// getFrameRegister - This method should return the register used as a base
377 /// for values allocated in the current stack frame.
378 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
380 /// getRARegister - This method should return the register where the return
381 /// address can be found.
382 virtual unsigned getRARegister() const = 0;
384 /// getLocation - This method should return the actual location of a frame
385 /// variable given the frame index. The location is returned in ML.
386 /// Subclasses should override this method for special handling of frame
387 /// variables and call MRegisterInfo::getLocation for the default action.
388 virtual void getLocation(MachineFunction &MF, unsigned Index,
389 MachineLocation &ML) const;
391 /// getInitialFrameState - Returns a list of machine moves that are assumed
392 /// on entry to all functions. Note that LabelID is ignored (assumed to be
393 /// the beginning of the function.)
394 virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const;
397 // This is useful when building DenseMaps keyed on virtual registers
398 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
399 unsigned operator()(unsigned Reg) const {
400 return Reg - MRegisterInfo::FirstVirtualRegister;
404 } // End llvm namespace